Time-to-Digital Converters
With ongoing technology scaling high resolution in the voltage domain becomes increasingly troublesome. Time domain resolution, however, is continuously improving as digital circuits become faster in each new technology generation. Time-to-Digital Convert
- PDF / 184,628 Bytes
- 9 Pages / 439.37 x 666.142 pts Page_size
- 109 Downloads / 283 Views
1. Abas, A., Bystrov, A., Kinniment, D., Maevsky, O., Russell, G., Yakovlev, A.: Time difference amplifier. Electronics Letters 38(23), 1437–1438 (2002). DOI10.1049/el:20020961 2. Abaskharoun, N., Roberts, G.: Circuits for on-chip sub-nanosecond signal capture and characterization. Custom Integrated Circuits, 2001, IEEE Conference on. pp. 251–254 (2001). DOI10.1109/CICC.2001.929766 3. Andreani, P., Bigongiari, F., Roncella, R., Saletti, R., Terreni, P., Bigongiari, A., Lippi, M.: Multihit multichannel time-to-digital converter with 1 Solid-State Circuits, IEEE Journal of 33(4), 650–656 (1998). DOI10.1109/4.663573 4. Chan, A., Roberts, G.: A deep sub-micron timing measurement circuit using a single-stage vernier delay line. Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002 pp. 77–80 (2002). DOI10.1109/CICC.2002.1012770 5. Chen, P., Liu, S.L., Wu, J.: A cmos pulse-shrinking delay element for time interval measurement. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on 47(9), 954–958 (2000). DOI10.1109/82.868466 6. Chen, P., Zheng, J.C., Chen, C.C.: A monolithic vernier-based time-to-digital converter with dual plls for self-calibration. Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005 pp. 321–324 (2005). DOI10.1109/CICC.2005.1568670 7. Corporales, L., Prefasi, E., Pun, E., Paton, S.: A 1.2-mhz 10-bit continuous-time sigmadelta adc using a time encoding quantizer. Circuits and Systems II: Express Briefs, IEEE Transactions on 56(1), 16–20 (2009). DOI10.1109/TCSII.2008.2008524 8. Daniels, J., Dehaene, W., Steyaert, M., Wiesbauer, A.: A/d conversion using an asynchronous delta-sigma modulator and a time-to-digital converter. In: Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on, pp. 1648–1651 (2008). DOI10.1109/ISCAS.2008. 4541751 9. Dhanasekaran, V., Gambhir, M., Elsayed, M., Sanchez-Sinencio, E., Silva-Martinez, J., Mishra, C., Lei, C., Pankratz, E.: A 20mhz bw 68db dr ct sigma delta adc based on a multibit time-domain quantizer and feedback element. In: Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, pp. 174–175,175a (2009). DOI10.1109/ISSCC.2009.4977364 10. Dudek, P., Szczepanski, S., Hatfield, J.: A high-resolution cmos time-to-digital converter utilizing a vernier delay line. Solid-State Circuits, IEEE Journal of 35(2), 240–247 (2000). DOI10.1109/4.823449 11. Helal, B., Straayer, M., Wei, G.Y., Perrott, M.: A low jitter 1.6 ghz multiplying dll utilizing a scrambling time-to-digital converter and digital correlation. VLSI Circuits, 2007 IEEE Symposium on pp. 166–167 (2007). DOI10.1109/VLSIC.2007.4342700
115
116
References
12. Helal, B., Straayer, M., Wei, G.Y., Perrott, M.: A highly digital mdll-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve subpicosecond jitter performance. Solid-State Circuits, IEEE Journal of 43(4), 855–863 (2008). DOI 10.1109/JSSC.2008.917372 13. Henzler, S.: Power Management of Digital Circu
Data Loading...
