Optical interconnection reverse data vortex network: performance analysis
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Optical interconnection reverse data vortex network: performance analysis R. G. Sangeetha · Vinod Chandra · D. Chadha
Received: 17 August 2012 / Accepted: 2 January 2013 / Published online: 19 January 2013 © Springer Science+Business Media New York 2013
Abstract Multistage interconnection networks are employed in data centres to interchange information between the processors and memory elements. Data Vortex (DV) is a multistage minimum logic network which can be used in data centres. DV satisfies the requirements of the interconnection networks such as scalability and throughput. However, the latency is on higher side, and reduction in latency can lead to higher throughput. In the present paper, we describe the feasibility and performance analysis of DV architecture in reverse direction. The routing and the possible hardware model of the node switch have been discussed. We present the performance analysis of Reverse Data Vortex (RDV) architecture in terms of throughput, latency and latency distribution. A comparative study with DV on throughput, latency and latency distribution is also presented. The simulation result shows that the decrease in latency of RDV is about 50 % that of DV and this leads to an increase in injection rate of RDV to values more than two times that of DV. Keywords Data Vortex · Latency · Reverse Data Vortex · Scalability · Throughput 1 Introduction The bandwidth demand of the traffic is increasing steadily at exponential rates. Large-scale high-performance routing R. G. Sangeetha · V. Chandra (B)· D. Chadha Department of Electrical Engineering, Indian Institute of Technology, New Delhi 110016, Delhi, India e-mail: [email protected] R. G. Sangeetha e-mail: [email protected] D.Chadha e-mail: [email protected]
systems, used for high data traffic, require high bandwidth and low latency interconnection networks. Multistage interconnection networks (MINs) have been studied extensively for switching in communication and parallel computing systems. Optical communication with photonic switching promises to meet the increasing demand in parallel processing systems. In most of the MINs, in the event of node failure, the switch fails to route in between the stages. In such situations, the packet needs to be rerouted to an alternate path to avoid network failure. The chained MINs find solution to route the packet to the desired destination through alternate paths. The multiple level minimum logic architecture proposed in [1] has the potential for providing such performance. The 2 × 2 Data Vortex (DV) switch is a high-speed low latency interconnection switch fabric [2] proposed by Yang et al. for the purpose of large-scale photonic interconnections. DV is a chained MIN, which provides alternate paths in the situation of failure or unavailability of switches in the intermediate stages. Also, the chained path is used as a virtual buffer for the incoming packet until it finds the desired path to reach the destination. DV satisfies the requirements of high throughput and scalability, maintainin
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