A High Radix Hierarchical Interconnection Network for Network-on-Chip
Architecture of the interconnection network has a great influence on the speed of the multi-core processor design. The main aims of any new architecture are to avoid the latency, and to decrease the cost. In this paper, we proposed new hierarchical interc
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Abstract Architecture of the interconnection network has a great influence on the speed of the multi-core processor design. The main aims of any new architecture are to avoid the latency, and to decrease the cost. In this paper, we proposed new hierarchical interconnection network, in order to build fast parallel computing system. We have evaluated the static network performance of the proposed network such as: node degree, diameter, cost, arc connectivity, bisection width, and wiring complexity. The proposed topology achieved low cost and small diameter comparing to 2D-mesh, and 2D-torus topologies. As well as, it gives good results in the other static parameters. Hence, the proposed network is good solution to improve the performance, and decrease the cost of the interconnection networks for the future generation parallel computing systems.
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Keywords Network-on-chip Interconnection network connection network Static network performance
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Hierarchical inter-
1 Introduction Architecture of modern computer systems should meet the advancement in technology, therefore, most of IT companies developed the architecture of network on chip (NoC), in order to improve the performance, and decrease the cost of these M.N.M. Ali (✉) ⋅ M.M.H. Rahman ⋅ R.M. Nor Department of Computer Science, KICT IIUM, Kuala Lumpur, Malaysia e-mail: [email protected] M.M.H. Rahman e-mail: hafi[email protected] R.M. Nor e-mail: [email protected] T.M.B.T. Sembok Cyber Security Center, UPNM, Kuala Lumpur, Malaysia e-mail: [email protected] © Springer International Publishing Switzerland 2016 P. Meesad et al. (eds.), Recent Advances in Information and Communication Technology 2016, Advances in Intelligent Systems and Computing 463, DOI 10.1007/978-3-319-40415-8_24
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networks. Network on chip composed of number of network clients: processors, DSPs digital signal processing, memories, peripheral controllers, gateways to networks on other chips, and custom logic, each client is placed in rectangular tile and communicates with all other clients by using the network resources [1]. Furthermore, the routers in NoC are similar in their performance to those routers in local area network, making their decisions based on routing algorithms. However, choosing the routing algorithm depends on the structure of NoC [2, 3]. It’s clear that, NoC is the basic architecture of parallel computing systems which provide efficient solutions for many of difficult problems in a reasonable time [4]. Interconnection networks of a multiprocessor computing system are a critical factor in determining the performance of the modern computing devices [5], due to their role in connecting processors and memories. In addition, the topology of these networks plays main role in determining the network diameter, whereas small diameter indicates low latency and good dynamic communication performance, leading to accelerate the speed of the system [6, 7]. New types of interconnection networks have been revealed to meet the advancement in signaling t
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