Optimisation of Junctions formed by Solid Phase Epitaxial Regrowth for sub-70nm CMOS
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Optimisation of Junctions formed by Solid Phase Epitaxial Regrowth for sub-70nm CMOS Richard Lindsay, Bartlomiej J. Pawlak1, Peter Stolk1, and Karen Maex IMEC, Kapeldreef 75, Leuven, B3001 Belgium. Philips Research Leuven, IMEC, Leuven, B3001 Belgium. ABSTRACT For the 70nm CMOS node, it is anticipated that conventional implantation and spike annealing approaches, even with pre-amorphisation and co-implantation, are unlikely to provide pMOS junctions consistent with the ITRS requirements. Here the junction performance is limited by equilibrium solid solubility. As laser annealing and in-situ doping techniques currently have unsolved integration problems, there is a renewed interest in using solid phase epitaxial regrowth (SPER) to form ultra-shallow metastable junctions. Such junctions have the potential to have an active dopant profile similar to the as-implanted profile. This offers above equilibrium solid solubility and abrupt profiles compatible with 70nm and even 45nm nodes. However there are concerns about residual defects, deactivation, diffusion and uniformity. In this paper we show how the Ge, F and B implant and SPER anneal can be optimised for abrupt, uniform and highly activated B junctions. There is latitude for higher doses and energies than conventional implants, however results show that this may lead to clustering causing enhanced deactivation and reduced mobility. We give attention to the probing issues involved in characterising partially annealed junctions. With this approach, p-type junctions having a sheet resistance of 265ohms/sq and depth of 22nm are realised which are compatible with 70nm and potentially 45nm CMOS nodes. INTRODUCTION Extending conventional implantation with spike anneal To optimise the performance of CMOS transistors there are certain restrictions placed on the junctions which extend underneath the gate. These restrictions are dictated by the International Roadmap for Semiconductors (ITRS) and are shown in figure 1 as a function of transistor gate length. In figure 1 the SEMATECH curve is included to show the limits of using B only and conventional RTA [1]. This curve is a collection of all the best results from literature as of 2001 and these junctions on the graph are almost always formed by high temperature spike anneals (>1050°C for 75°C/s and ramp down >50°C/s) in
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