Materials Challenges for CMOS Junctions
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Materials Challenges for CMOS Junctions William J. Taylor, Michael J. Rendon1, Eric Verret1, Jack Jiang, Cristiano Capasso, Dave Sing, Jen-Yee Nguyen, James Smith, Eric Luckowski, Arturo Martinez, Jamie Schaeffer, Phil Tobin Motorola Advanced Products R&D Lab, 1Motorola CMOS Platform Device Development Mail Drop K-10, 3501 Ed Bluestein Blvd., Austin, Texas, USA 78721 Abstract Against a backdrop of the latest ITRS predictions for CMOS junctions, we compare methods for dopant introduction and activation, methods for making contact to these regions, and methods for measurement of material and device properties. As activation without diffusion (sub-melt laser, capacitor discharge flash, or solid phase epitaxy) becomes more feasible, the burden on Xj, Rsh and abruptness falls on the implanters, and the process margin appears slim, opening the door for other methods of doping. For contact resistance, a major component of transistor parasitics, we find that either a move to a different substrate, or from a single midgap silicide to two band-edge metals/silicides can be quite beneficial. Through the use of simple test structures, we describe a means of extracting each component of the parasitic resistance, facilitating development of materials for CMOS junctions. Introduction While the past ten or more years of CMOS junction development have been addressed primarily through variations to the conventional implant-and-anneal-in-Si, the next ten will likely involve modifications to both the material systems and their manner of introduction. Complicating these changes is the expectation that the channel and the gate stack material systems will simultaneously be undergoing revolutionary change, with a likely need to avoid interdiffusion or recrystallization, and thus can be expected to put an upper limit on the thermal budget allowed in the CMOS front end. To meet these demands, recent developments in anneal schemes provide the promise of activation without diffusion, which immediately shifts the burden of Xj and abruptness scaling requirements to the implanters; we therefore investigate the feasibility of these tools to meet this challenge. Regarding contacts to the doped regions - the shift from CoSi2 to NiSi facilitates current CMOS integration concerns, but its temperature limits can be restrictive as one looks to 3-D integrations later in the decade. Another option on the horizon - separate metals/silicides for low-resistance contacts to the N+/P+ regions - becomes worthy of study. If one questions role of materials in CMOS in the next few years, one can simply observe the trend for the rate of introduction of new materials over the history of MOS development. The left side of Figure 1 shows the new materials introduced in the current and past 3 decades. The rate of increase in materials introduction is obvious. The right side of Figure 1 shows the different means of delivering those materials, and the same trend emerges: whereas the early years were dominated by oxidation and CVD furnaces and implanters, the upcomi
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