Optimising the Rectification Ratio of Schottky Diodes in n-SiC and n-Si by TCAD
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Optimising the Rectification Ratio of Schottky Diodes in n-SiC and n-Si by TCAD Hiep N. Tran1, Tuan A. Bui1, Geoff K. Reeves1, Patrick W. Leech1, Jim G. Partridge2, Mohammad S. N. Alnassar1, Anthony S. Holland1 1 2
School of Engineering, RMIT University, Melbourne, Victoria, 3001, Australia School of Applied Sciences, RMIT University, Melbourne Victoria, Australia
ABSTRACT Finite element modelling has been used to optimise the current/ voltage (I/V) characteristics of metal/ n-SiC and metal/ n-Si diodes incorporating a thin interfacial layer. The electrical properties of the diodes have been examined in relation to the polytype of SiC (3H, 4H or 6C), the doping level, NA, (1015 - 1018cm3) of the substrate, the defect state density, Dit and the work function of the Schottky metal, Φm. The modelling by Technology Computer-Aided Design (TCAD) has shown that the presence of an interfacial insulating layer with a thickness of 1.0 nm has reduced the reverse leakage current of the diode by a factor of ~102 in Si and 1013 (from 10-19 A to 10-6 A) for SiC with only a minor reduction (~ 0.8 times) in the forward current in SiC. The properties of the diodes have been modelled at room temperature without thermal annealing. INTRODUCTION Schottky barrier diodes (SBDs) based on SiC have shown greater resistance to high power and elevated temperatures than silicon-based switching devices. However, the performance of these SBDs has depended critically on the quality of the metal/ n-SiC or n-Si interface. The use of chemical etches such as buffered HF to remove native oxide from n-Si prior to deposition of the metal layer has resulted in inhomogeneity in the Schottky barrier height across the surface [1]. A more reliable method of stabilising the electrical properties of SBDs has been the incorporation of a thin insulating layer of dielectric at the interface with similar effects reported both experimentally [2] and by modelling [3]. The beneficial effect of the interfacial layer has been attributed to an increase in the mean tunnelling barrier and in the apparent barrier height [3]. The deposition of a thin interfacial layer in metal/Si and carbon/n-Si diodes has produced diodes of very high quality [4]. Similarly, in metal/ n-SiC diodes, the forward current/ voltage characteristics have been identified as highly sensitive to the pre-metallisation treatment [5]. The controlled growth of an interfacial layer of SiO2 on the surface of n-SiC has resulted in an increase the uniformity of properties of the Schottky diodes [6]. However, a relatively high density of interface traps, Dit, has typically accompanied the deposition of a layer of SiO2. An attempt to lower the value of Dit has encouraged the use of alternative layers of dielectric consisting of nitride [7] or bi-layers of SiO2/ nitride [8] and AlNx/ SiO2 [9]. In this paper, we have used modelling with a Technology Computer-Aided Design (TCAD) program to optimise the structure of metal/ n-SiC and metal/ n-Si diodes incorporating a thin insulating layer. The effect of the insula
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