Optimizing the Screen-Grid Field Effect Transistor for high drive current and low Miller capacitance
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Optimizing the Screen-Grid Field Effect Transistor for high drive current and low Miller capacitance Y.Shadrokh1, K.Fobelets1, J. E. Velazquez-Perez2 1 Imperial College of London, Department of Electrical and Electronic Engineering, Exhibition Road, London SW7 2BT, UK 2 Universidad de Salamanca, Departmento de Física Aplicada, Edificio Trilingüe, Pza de la Merced s/n, E-37008 Salamanca, Spain
ABSTRACT Reduction of parasitic capacitances and improvement of the on-off current ratio (ION/IOFF) can be achieved by increasing the gate control in Field Effect Transistors (FETs). Multiple gated FETs (MugFETs) lend themselves well for this. The MugFET investigated in this manuscript is the Screen Grid FET (SGrFET) that consists of multiple gate cylinders inside the channel perpendicular to the current flow. In this work we illustrate, using 2D Technology Computer Aided Design (TCAD), that the multiple geometrical degrees of freedom of the SGrFET can be exploited to simultaneously optimise the on-current, ION and the gate-drain Miller parasitic capacitance for increased switching speed. INTRODUCTION The Screen Grid Field Effect Transistor (SGrFET) is an alternative multi-gated FET (MugFET) [1]. The SGrFET is defined on SOI (Silicon-On-Insulator) substrates and has a nontraditional gating geometry, illustrated in fig. 1. The gate consists of multiple cylindrical cavities with a thin thermal oxide sidewall and a poly-Si or metal filling. These gate cylinders (fingers) are standing perpendicular to the current flow in the SOI body (channel). Different gate cavity configurations are possible [1]. Highly doped source and drain areas are located at both sides of the device and have the same width as the device, avoiding contacting problems to small areas. For optimum performance the channel doping is low to un-doped in order to preserve high mobility values and is of the same doping type as the contact regions, unlike in traditional MOSFETs [2]. The device operation is essentially MESFET-like (Metal Semiconductor FET) – the channel width is determined by the extension of the depletion between two gate cylinders in the same row. The role of the second row of gate fingers (near the drain) is to effectively control short channel effects. The SGrFET outperforms other MOSFET structures in the sub-threshold and weak inversion regions, because in these regimes the carriers have higher mobilities. The multiple geometrical degrees of freedom of the SGrFETs reduce the parasitic gate-drain capacitance and improve the sub-threshold slope. These make the SGrFET suitable for digital applications with improved switching speed and improved gate control over the channel. In this paper all the simulations are carried out using a 2D Technology Computer Aided Design (TCAD) device simulator, MediciTM [3]. In the first section we show how changing the device structure improves rise and fall times. The second section shows how to improve ION and IOFF in P-type devices for CMOS circuits. The technique improves the rise time in the output vol
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