P Channel Mosfet Devices in Nanocrystalline Silicon
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0910-A22-07
P Channel Mosfet Devices in Nanocrystalline Silicon Durga P. Panda1, Max Noack1, and Vikram Dalal 2 1 Microelectronics Res. Center, Iowa State University, ASC1, Ames, Iowa, 50011 2 Electrical and Comp. Engr., Iowa State University, Coover Hall, Ames, Iowa, 50011 ABSTRACT We report on the growth and properties of p-channel nanocrystalline Si thin film transistor (TFT) devices. In contrast to previous work, the devices are fabricated in n-body nanocrystalline Si. The doping of the n-body is systematically changed by doping with ppm levels of phosphorous. The threshold voltage was found to change systematically as phosphorus content increased. The TFT devices are of the bottom-gate type, grown on oxidized Si wafers. Source and drain contacts were provided by using either plasma grown p type nanocrystalline layers, or by the simple process of Al diffusion. A top layer of plasma-deposited silicon dioxide was found to decrease the off current significantly. High on-off current ratios exceeding 106 were obtained. Hole mobilities in the devices were consistently good, with the best mobility being in the range of ~1.3 cm2/V-s. INTRODUCTION TFT devices are very important for display purposes and for wearable electronics. Two types of TFT devices have been widely researched : amorphous Si:H (a-Si:H) TFT devices [1,2] and nanocrystalline Si:H (nc-Si:H) TFT devices [3-6]. Only n-channel devices can be made in the a-Si:H material system because of the very low mobility of holes in that material. In nc-Si:H system, both n and p type devices have been made, but most of the work has concentrated on making only the n channel devices [3-5]. p-channel devices made at higher temperatures on steel substrates, show good mobility values, ~ 20 cm2/V-s [6], but when the devices are made at lower temperatures which are compatible with plastic substrates, for example, the mobility values tend to be low, ~0.1 cm2/V-s, in contrast to n channel devices, where high mobilities (>50 cm2/V-s) have been obtained [3]. Also, all the previous work has been on making devices on supposedly undoped nc-Si:H materials where the Fermi level lies supposedly in the middle of the gap. Such supposedly undoped materials, in reality, have significant amorphous phase in them, which contributes to a higher resistivity, and therefore, it is not surprising that the hole mobilities in devices are low, being more characteristic of amorphous rather than nanocrystalline materials. The standard p channel MOSFET device relies on having an n-body, where the source-body p-n junctions prevent any significant current flow from source to drain unless a channel inducing gate voltage is present. Thus, the ideal p channel nc-Si:H device should also use such a structure with a channel layer that is formed in nanocrystalline material and not in mainly amorphous materials. In this paper, we study the fabrication of bottom gate p-channel devices on oxidized Si wafers where the body is deliberately doped n type. Also, we show that crystallinity can be achieved in a layer clos
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