Parallel and Serial Concatenated Single Parity Check Product Codes
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Parallel and Serial Concatenated Single Parity Check Product Codes David M. Rankin Department of Electrical and Computer Engineering, University of Canterbury, Private Bag 4800, Christchurch, New Zealand Email: dave [email protected]
T. Aaron Gulliver Department of Electrical and Computer Engineering, University of Victoria, P.O. Box 3055, STN CSC, Victoria, BC, Canada V8W 3P6 Email: [email protected]
Desmond P. Taylor Department of Electrical and Computer Engineering, University of Canterbury, Private Bag 4800, Christchurch, New Zealand Email: [email protected] Received 12 June 2003; Revised 9 April 2004 The parallel and serial concatenation of codes is well established as a practical means of achieving excellent performance. In this paper, we introduce the parallel and serial concatenation of single parity check (SPC) product codes. The weight distribution of these codes is analyzed and the performance is bounded. Simulation results confirm these bounds at high signal-to-noise ratios. The performance of these codes (and some variants) is shown to be quite good given the low decoding complexity and reasonably short blocklengths. Keywords and phrases: parallel and serial concatenation, single parity check product codes.
1.
INTRODUCTION
The parallel and serial concatenation of codes is well established as a practical means of achieving excellent performance. Interest in code concatenation has been renewed with the introduction of turbo codes [1], otherwise known as parallel concatenated convolutional codes (PCCCs) [2], and the closely related serially concatenated convolutional codes (SCCCs) [3]. In this paper, we introduce the parallel and serial concatenation of single parity check (SPC) product codes. These codes perform well and yet have a low overall decoding complexity. Similar work involving parallel concatenation of SPC codes (not SPC product codes) has been considered in [4], while serially concatenated SPC codes are investigated in [5]. It should be noted that the component codes are not recursive and therefore both the parallel concatenated code (PCC) and the serially concatenated code (SCC) should not exhibit any “interleaver gain” [2, 3]. However, in practice, the parallel and serial concatenation of nonrecursive codes can still perform very well, for example, the “turbo block code” [6]. It will be shown that parallel and serially concatenated
SPC product codes also perform well, especially considering the very low decoding complexity. The main reason for this good performance is the relatively small number of lowweight codewords. The weight distribution and performance bounds will be investigated in Section 5. 2.
ENCODING THE PCC AND SCC
In general, a parallel concatenated code involves encoding a set of common data bits between multiple component codes, typically the data bits are interleaved between the component encoders. The component codes used throughout this paper are {n, d} SPC product codes, where d is the number of dimensions and n is the length of the SPC codes in every dim
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