Partial Reconfiguration and Hierarchical Design
Partial Reconfiguration takes advantage of hierarchical design capabilities available in the Xilinx Vivado Design Suite. This chapter describes the various designs that can benefit from the use of Partial Reconfiguration, as well as the key concepts and d
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Partial Reconfiguration and Hierarchical Design Amr Monawir
Partial Reconfiguration takes advantage of hierarchical design capabilities available in the Xilinx Vivado Design Suite. This chapter describes the various designs that can benefit from the use of Partial Reconfiguration, as well as the key concepts and design considerations for Partial Reconfiguration and the other hierarchical design flows available.
19.1
Partial Reconfiguration
FPGA technology provides the flexibility of programming and reprogramming a device with a modified design in the field without the need to go through refabrication. Partial Reconfiguration takes this one step further, allowing the dynamic modification of part of an operating FPGA design without impacting the rest of the design.
19.1.1
Applications
Any system with functions that can be time-multiplexed stands to benefit from taking advantage of Partial Reconfiguration. Using Partial Reconfiguration allows functions to be switched on hardware, similar to a microprocessor’s ability to switch between tasks in software.
A. Monawir (*) Xilinx Ireland, Dublin, Ireland e-mail: [email protected] © Springer International Publishing Switzerland 2017 S. Churiwala (ed.), Designing with Xilinx® FPGAs, DOI 10.1007/978-3-319-42438-5_19
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Fig. 19.1 100G Muxponder design implemented without and with partial reconfiguration
19.1.1.1
Multi-protocol Networking
In optical transport network (OTN), client side ports need to support multiple interface protocols. To ensure this, every possible interface protocol has to be independently implemented for each port. This is resource intensive and inefficient, especially considering that only one protocol will be used per port at any one time. Partial Reconfiguration allows the different protocols for each port to be dynamically loaded on demand. This removes redundant logic and provides a more efficient use of resource to implement the same functionality. Figure 19.1 shows the same 100G Muxponder system implemented with and without Partial Reconfiguration.
19.1.1.2
SW-Controlled HW Coprocessing
Hardware coprocessing is achieved by off-loading compute-intensive functions from the central processor to a coprocessor or dedicated hardware, which executes the function with lower power and latency. Image and video coprocessing is a typical example of this approach. Having dedicated hardware for each function is an inefficient use of resources. Partial Reconfiguration allows a library of hardware functions to be partially reconfigured onto the same set of FPGA resources as and when required. Figure 19.2 gives an example of a processor system, with an array of dedicated hardware coprocessing functions, implemented with and without the use of Partial Reconfiguration.
19 Partial Reconfiguration and Hierarchical Design
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Fig. 19.2 A microprocessor system with dedicated hardware coprocessors implemented without partial reconfiguration on the left and with partial reconfiguration on the right
19.1.1.3
Security and Encryption
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