Performance Control of High Mobility, Printed Thin Film Transistors using Semiconducting Nanotube Ink
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Performance Control of High Mobility, Printed Thin Film Transistors using Semiconducting Nanotube Ink N. Rouhi, D. Jain, K. Zand, and P. J. Burke Electrical Engineering and Computer Science, University of California-Irvine, Irvine, CA, U.S.A [email protected]
In this work, we present progress towards device fabrication using purified, semiconducting-enriched SWNT as the base material. Nanotubes were deposited in different densities (low, moderate, and high density) with different gate length of transistors and effect of each parameter has been studied using DC measurements. It is been shown that the nanotube network density plays a significant role in controlling the performance of such devices. By controlling the density of nanotubes in the network, we laid down a road map to predict and enhance the device performance based on their mobility and on/off ratio. From this work the DC analysis of devices characterization shows a mobility more than 90 cm2/V-s and also on/off ratios as high as, 105 have been achieved. We have demonstrated the first density-control technique over the nanotube network as a key point to modify the transistor’s mobility and on/off ratio [1]. When dense network mats of nanotubes were deposited, devices outperformed with higher mobility more than 90 cm2/V-s, enabling a faster switching speed. While relatively low-density mats yielded devices with on/off ratio of more than 105, which makes this technique feasible for low power nanoelectronics. Besides, the effect of various gate lengths have been studied which reveals an interesting trend between the channel length and the mobility. I.
FABRICATION
Semiconducting single-walled nanotube (purified 99%) network was deposited on top of Si/SiO2 substrate. Surface modification (APTES) was also used to ensure the absorption of semiconducting tubes. The nanotube ink was made using density gradient centrifugation process for the separation of nanotubes with different chiralities. Nanotube solution was then poured on wafers. The impact of density of nanotube network was studied for a comprehensive range of densities. Following the nanotube deposition, the wafer was patterned for source and drain deposition using standard photolithography. We also studied the effect of gate length (10~100 µm) on mobility and on/off ratio. E-beam evaporation was used to deposit source and drain electrodes (Pd/Au). The Si wafer acts as the back gate and 300 nm of SiO2 was used as the gate dielectric. Figure 1 shows the schematic of fabrication process and SEM of nanotube network.
Fig. 1. Fabrication process and SEM image of nanotube network
II. ELECTRICAL MEASUREMENTS The ID-VD extracted from the dc measurement shows that the current-voltage relationship is linear for small VD ranging from -1 V to 1 V (triode region), indicating good ohmic contact between nanotubes and electrodes (Pd/Au). By applying more negative VD the devices clearly show saturation behavior. Using 99% semiconducting nanotube network results in high on/off ratio for low and moderate tube densities and
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