Point Defects in a Directly-Bonded Wafer, and its Comparison with the Bonded SOI Wafers
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POINT DEFECTS IN A DIRECTLY-BONDED WAFER, AND ITS COMPARISON WITH THE BONDED SOI WAFERS
Akira USAMI, Keisuke KANEKO, Akira ITO, Shun-ichiro ISHIGAMI* and Takao WADA. Nagoya Institute of Technology, Nagoya 466, Japan. "Mitsubishi Materials Co.,Ltd., Omiya 330, Japan.
Directly-bonded wafers were characterized using capacitance-voltage (C-V) and deep level transient spectroscopy (DLTS) measurements. We also studied silicon on insulator (SOI) wafers with different interfacial oxide thicknesses. In the active layers of the directly 23 gm bonded wafer, two dominant electron traps (Ec-0. 16eV, Ec-0.24eV) were observed at from the bonded interface. Both trap densities are almost constant (about 2 x 101 1cm- 3 ) at distances larger than about 103 gm. In the substrate, the density of the shallower electron trap increases (about 8 x 10'1 cm- ) within about 20 gm from the interface, while the other trap concentration is almost constant and nearly equal to that in the active layers. No trap was observed near the wafer backside. These traps were also observed in the bonded SO1 wafers. Both the trap concentrations depend on the thickness of the bonded interfacial oxide. The shallower trap concentration increases with increasing oxide thickness, and the deeper one decreases.
The technique for bonding two wafers without any adhesive is one of the nextgeneration device techniques. This technique can be used in various device fabrications. However the bonding technique is not completely established. It has been reported that there are SiOx layers near the bonding interface[l]. The charge at the interface degrades the electrical properties near the bonded interface[2][3]. The bonded wafers have been extensively evaluated with the structural measurements such as TEM[4]. There are a few reports of the electrical properties of the bonded wafers. We previously measured the electrical properties of the bonded SO1 wafers using deep level transient spectroscopy (DLTS) method[5] and found that there are an unstable electron trap in the bonded SOl wafer with voids and two stable traps in the wafer without any void. In this study, we investigated the electrical properties of the directly-bonded wafer and the bonded SOl wafers without any void.
We prepared a directly bonded wafer and three bonded SO1 wafers with different interfacial oxides thicknesses (0.01,0.1,0.75 /im). The sample structure is shown in Fig. 1. Two Si ingots were prepared, the wafers for the active layers were from one of these ingots and the wafers for the substrate were from the other one. The resistivity of the active layers is 45 to 48.8 Q-cm and that of the substrate 8 to 8.5 Q.cm. The thickness of the active layers is about 23 gm. No void was observed in all the samples by the ultra sonic flow detection method. The wafers for the substrate were bent slightly and bonded with the wafers for the active layer at room temperature. For the bonded SOI wafers, thermal oxide layers were grown on the Si wafer for the active layers before bonding. In order to bond completely
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