Polycrystalline Silicon-Germanium Electrode Contact Technology Improvement for MEMS Applications
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1222-DD04-03
Polycrystalline Silicon-Germanium Electrode Contact Technology Improvement for MEMS Applications Gert Claes1, 2, Simone Severi1, Stefaan Decoutere1, Jean-Pierre Celis2 and Ann Witvrouw1 1 CTI, IMEC, Kapeldreef 75, B-3000 Leuven, Belgium; 2 MTM, K.U.Leuven, Kasteelpark Arenberg 44, B-3001 Heverlee, Belgium. ABSTRACT Poly-SiGe has quite some potential as structural MEMS layer for CMOS-MEMS integration. However, the contact resistance between SiGe MEMS and top CMOS metal should be low to avoid parasitic effects that would reduce the system performance. In this paper, a new and simple approach is proposed to achieve a low contact resistance between a top CMOS interconnect and a boron doped poly-SiGe MEMS layer deposited at 450 °C. The use of a 20 nm soft sputter etch in combination with a Ti-TiN (5-10 nm) interlayer results in a contact resistivity of 6.2 ± 0.4 x 10-7 Ωcm2 that is lower than previously reported. The uniformity of the contact resistivity across the wafer is also better than the state-of-the-art value.
INTRODUCTION Polycrystalline Silicon-Germanium (poly-SiGe) has shown to be a promising structural material for microelectromechanical systems. SiGe resonators [1], bolometers [2], cantilevers for data storage, mirrors and gyroscopes have already been demonstrated. Moreover, SiGe enables CMOS-MEMS integration due to its low, CMOS-compatible deposition temperature (≤ 450 °C) [3, 4]. While the mechanical and electrical properties of the SiGe layer itself have been intensively studied [5], the electrical contact between MEMS device and CMOS substrate is of uttermost importance. A low resistive contact between poly-SiGe and CMOS top metal layer (Figure 1) is needed for a successful monolithic CMOS-MEMS integration with low interconnect parasitic resistance. Eyoum et al. [6] proposed a Ni-silicide process to achieve low contact resistances. The aim of this work is to improve the contact quality without the use of a complex, and thus costly, silicide process.
Figure 1: Example of a CMOS-MEMS integration cross-section
To connect the MEMS bottom electrode to the CMOS top metal, a via through the CMOS passivation is defined by lithography, an RIE etch, and a resist removal step. The resist strip normally consists of a wet chemical etching step and a dry etching process including the use of
an oxygen plasma to remove all polymers. During the oxygen plasma exposure, the contact interface can oxidize, resulting in a non-ohmic behaviour of the contact (Figure 2a). The oxidized interface layer (IL), identified as a mixture of TiO2 and SiO2 by energy dispersive X-ray spectroscopy (EDS), was clearly observed by transmission electron microscopy (TEM) (Figure 2b).
Figure 2: (a) Example of the behaviour of a non-ohmic contact; (b) TEM picture of the SiGe - AlCu-TiN interface in which the thin interface layer (IL) is visible
The contact resistance between boron doped SiGe films and AlCu(0.5%)-TiN films was investigated for different contact cleaning treatments, SiGe recipes, and optional interfacial layers.
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