Porous Organosilicates for On-Chip Dielectric Applications
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decreases in wiring dimensions and pitches. The calculated RC delays of the interconnects depend on the resistivity of the metal lines, and the dielectric constant of the on-chip insulators as well as the length and pitch of the wiring interconnects) As shown in Figure 1, increasing the wiring densities will trigger unwanted increases in signal delay unless accompanied by simultaneous decreases in metal resistivity and/or the dielectric constant of the insulating media. Figure 1 shows the calculated signal delays for AI(Cu) and Cu interconnects and the current silicon dioxide insulator (k = 4.0) versus those of a hypothetical material with k = 2.0. Recently, reliability studies on multilevel devices prepared in a manufacturing environment demonstrated that traditional aluminum/copper wiring may be replaced by copper, resulting in an approximately 40% decrease in the metal interconnect resistivity,3 and it is clear that this innovation will be incorporated in future advanced devices.4 This alone, however, will not sustain the proposed scaling of future devices without subsequent decreases in the dielectric constant of the insulator. Realization of lower dielectric constants in the interconnect insulators will also improve power consumption, an additional chip performance issue. It is clear that in order to maintain scaling in future devices, simultaneous advances will be required in many areas including device design, lithographic processes, metal interconnect resistivity and dielectric insulators. While innovative approaches to the first three issues have progressed, it is clear that materials research on low k insulators has lagged somewhat behind.
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Figure 1: Calculated delays for aluminum and copper interconnects. This situation is exacerbated by the daunting materials requirements resulting from the long-term, systematic optimization of semiconductor integration criteria based on silicon dioxide insulators. Progress in new dielectrics is further complicated by the uncertainty of whether advanced dielectric insulators will be deposited by vapor phase deposition (CVD) techniques or will be applied by solution spin-on procedures. The former has a long and successful history, but seems to suffer from uncertain extendibility to ultra low k materials (k < 2.2). The latter, in spite of its track record for photoresists, has raised some questions in applications to on-chip dielectric insulators. What seems clear, however, is that switching back and forth between different deposition techniques for new device generations is not an attractive option. In spite of the uncertainty regarding the preferred method f
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