Power-Aware Testing and Test Strategies for Low Power Devices
Power-Aware Testing and Test Strategies for Low-Power Devices Edited by: Patrick Girard, Research Director, CNRS / LIRMM, France Nicola Nicolici, Associate Professor, McMaster University, Canada Xiaoqing Wen, Professor, Kyushu Institute of Technology, Jap
- PDF / 263,344 Bytes
- 20 Pages / 439.37 x 666.142 pts Page_size
- 32 Downloads / 314 Views
Patrick Girard
•
Nicola Nicolici
•
Xiaoqing Wen
Editors
Power-Aware Testing and Test Strategies for Low Power Devices
ABC
Editors Patrick Girard LIRMM / CNRS Laboratoire d’Informatique de Robotique et de Micro´electronique de Montpellier 161 Rue Ada 34392 Montpellier France [email protected]
Xiaoqing Wen Department of Computer Science and Electronics Kyushu Institute of Technology 680-4 Kawazu Iizuka 820-8502 Japan [email protected]
Nicola Nicolici Department of Electrical and Computer Engineering McMaster University 1280 Main Street West Hamilton ON L8S 4K1 Canada [email protected]
ISBN 978-1-4419-0927-5 e-ISBN 978-1-4419-0928-2 DOI 10.1007/978-1-4419-0928-2 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2009930470 c Springer Science+Business Media, LLC 2010 ° All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Summary and Objective of the Book
Power dissipation is becoming a critical parameter during manufacturing test as the device can consume much more power during test than during functional mode of operation. In the meantime, elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low-power devices. This book provides knowledge in this area. It is organized into three main parts. The first one gives necessary background and discusses issues arising from excessive power dissipation during test application. The second part provides comprehensive knowledge of structural and algorithmic solutions that can be used to alleviate such problems. The last part surveys lowpower design techniques and shows how these low-power devices can be tested safely without affecting yield and reliability. EDA solutions for considering power during test and design-for-test are also described in the last chapter of the book.
v
About the Editors
Patrick Girard received a M.S. degree in Electrical Engineering and a Ph.D. degree in Microelectronics from the University of Montpellier,
Data Loading...
