Process Control Challenges and Solutions: TEOS, W, and CU CMP
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ABSTRACT Various options that afford control of the TEOS, W, and Cu/barrier polishes were explored in the building of multilevel dual inlaid structures. Improved tool performance that enables more sophisticated down pressure control with higher resolution backpressure adjustments was employed for the oxide module to control the interlevel capacitances. Planarity at both the global and local levels at the oxide polish affords a good starting point for successive builds without metal pooling. In W CMP, small and controllable oxide erosion and plug recess was obtained with harder polishing pads. In Cu/barrier CMP, the tight overpolish/underpolish margin was maintained by head control and appropriate endpoint algorithms. A six-level build with tight and low sheet resistances and leakages was demonstrated. INTRODUCTION In inlaid logic devices there is a move away from oxide to metal CMP for more levels of build. However, the process control required for the oxide/W polish levels is tighter because of the requirement of a high degree of planarity from the upper inlaid metal layers. For Cu, a tight polish window with controlled over/under polish has to be maintained at all metal levels for a successful multilevel structure build. EXPERIMENTAL All the tests were carried out on 8" wafers on commercially available one head dual platen and three head four platen CMP tools. The film rates and uniformities were measured on a Tencor UV1250 and a four point probe RS55. For this set of experiments, a KOH-based slurry was used for TEOS polish, ferric nitrate based for W, and a proprietary slurry for Cu/barrier CMP. The monitoring of the oxide erosion was done by oxide thickness and profile measurements. In addition, electrical measurements were conducted on selected patterns to monitor leakage and contact resistance. With W CMP, oxide erosion tests were conducted on two device types (Logic and SRAM), four different mask sets with successively finer technology design rules, viz. 0.25pm, 0. 18pm, and 0. 13pm. Across wafer pattern density effects could be evaluated at different line widths. On the 0.1 8pm and 0. 13prn sets, three different pattern densities at the local interconnect level were evaluated. The first, called dens 1 (contact chains), had the lowest
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pattern density. The second, called dens2 (local interconnect pattern), had an intermediate density level; while the third, called dens3 (process control structures comprised of large serpentine combs at the local interconnect level), had the highest pattern density. RESULTS AND DISCUSSION In oxide CMP, the greatest challenge is to have a uniform post-polish thickness within and across wafers. Figure 1 shows a cross-section schematic after polish. It is simplified to display the effects of CMP on electrical parameters. With oxide polish, maintaining a uniform post-CMP thickness within and across wafers ensures that one would sustain a tight distribution of interlevel capacitances. Various strategies ca
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