Programmed substrate temperature ramping to increase nucleation density and decrease surface roughness during metalorgan
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Programmed substrate temperature ramping to increase nucleation density and decrease surface roughness during metalorganic chemical vapor deposition of aluminum R. Jonnalagadda Allied Signal Inc., 3520 Westmoor Street, South Bend, Indiana 46628-1373
D. Yang Department of Chemical Engineering, Rensselaer Polytechnic Institute, Troy, New York 12180
B. R. Rogers Department of Chemical Engineering, Vanderbilt University, Nashville, Tennessee 37235
J. T. Hillman and R. F. Foster Tokyo Electron Arizona, 2120 West Guadalupe Road, Gilbert, Arizona 85233-2805
T. S. Cale Department of Chemical Engineering, Rensselaer Polytechnic Institute, Troy, New York 12180 (Received 16 March 1998; accepted 18 December 1998)
We discuss substrate temperature ramping effects during chemical vapor deposition of aluminum on nucleation density, texture, surface roughness, and resistivity of the resulting films. Results from three different process protocols are presented. Ramping the temperature down during the deposition from 673 K resulted in a larger fraction of small nuclei compared to deposition at a constant temperature of 573 K. From among the protocols studied, the lowest surface roughness was obtained by initially depositing for a short time while ramping the temperature down from 673 K, followed by deposition at 573 K, compared to all the other films. The same process protocol resulted in the highest Al(111) texturing, highest reflectivity, and lowest resistivity.
I. INTRODUCTION
Shrinking device dimensions in the microelectronics industry are increasing the complexity of “back end” processes, those used to build the multilevel metallization stacks that interconnect devices. Each new device generation includes more metal layers. Vertical dimensions are currently being scaled at a slower rate than the lateral dimensions, which naturally increases via aspect ratios. Highly conformal chemical vapor deposited (CVD) tungsten has been used for several years to fill higher aspect ratio vias.1 Sputtered (PVD) aluminum alloys are used to form the longer current carrying lines. While this combination of CVD tungsten and PVD aluminum alloys is manufacturable, there are several reasons why CVD aluminum would be an attractive substitute for the CVD tungsten in vias. The most obvious reason is the much lower resistivity of aluminum s2.7 mV cmd compared to that of tungsten (5.7 mV cm). Also, the interface between the PVD aluminum alloy lines and the CVD tungsten via plugs is a site for electromigration failures.2 CVD aluminum is made more electromigration resistant by alloying it with copper.3 The use of CVD aluminum alloyed with CVD Cu to fill inlaid structures has been reported.4 If these materials can be used successfully in 1982
http://journals.cambridge.org
J. Mater. Res., Vol. 14, No. 5, May 1999
Downloaded: 21 Mar 2015
a dual-inlaid process scheme, a significant reduction in the number of back end process steps is possible. Simmonds and Gladfelter5 reviewed CVD aluminum research that wa
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