Pseudo-MOS Operation of Ultra-Narrow Polycrystalline Silicon Wires: Electrical Characterization and Memory Effects
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Pseudo-MOS Operation of Ultra-Narrow Polycrystalline Silicon Wires: Electrical Characterization and Memory Effects C. Anghel, N. Hefyene, A.M. Ionescu, M. Declercq, J.W. Tringe 1 , J.D. Plummer1 Swiss Federal Institute of Technology Lausanne, Electronics Laboratory, ELB Ecublens, CH-1015, Lausanne, Switzerland 1 Center for Integrated Systems, Stanford University, Stanford, CA 94305-4070, U.S.A. ABSTRACT This paper presents a new method for the electrical characterization of polycrystalline silicon wires based on the pseudo-MOS effect. The investigated devices are ultra-narrow (0.10.2µm), four-contact polycrystalline silicon wires composed of several individual grains in series. The pseudo-MOS static operation allow the examination of interface and bulk characteristics via MOSFET modeling in terms of electrical parameters (carrier mobility, flat band and threshold voltages, mobility reduction coefficient). Additionally, the measurement of 1/f noise is shown to be a useful complementary characterization tool for material investigation. Particular attention is paid to the exploration of transient phenomena in the dynamic pseudoMOS operation. A significant I-V hysteresis is experimentally revealed when high voltages are applied on the substrate acting as a gate. Long current relaxation (>100s) in accumulation and depletion, in darkness and under illumination, demonstrate the dominance of carrier trapping at grain boundaries over oxide charging and/or SRH generation-recombination intra-grain phenomena. The dynamic regime analysis shows remarkable data retention duration and suggest further investigations of polycrystalline silicon wires for memory applications may be useful. INTRODUCTION In recent years, particular attention has been paid to polycrystalline silicon thin-film transistors because of their potential applications for LCD and high density SRAM [1-3], [5]. Because typical device dimensions approach now the size of the polycrystalline silicon grains, individual grain boundary properties begin to be more dominant [4] and the blanket film approach, which reflects average material properties, becomes obsolete. This paper presents a novel, simple yet powerful, electrical characterization method based on the in situ pseudo-MOS operation of ultra-narrow polycrystalline silicon wires made of several individual grains in series. Static and dynamic measurements combined with 1/f noise analysis were carried out in pseudo-MOS regimes (accumulation and depletion) in polycrystalline silicon wires made of a few grains, from room temperature up to 150°C. Together with modeling work, these measurements and analyses provided unique insight in the specific conduction mechanisms in polycrystalline silicon. In particular, hysteresis effects and long relaxation phenomena were observed and analyzed. EXPERIMENT: STATIC PSEUDO-MOS OPERATION Test structures are four-contact, boron-doped (~5x1017 cm-3), ultra-narrow (W~0.1-0.2µm) polycrystalline silicon wires (CVD deposited at 623°C, on top of a 5500Å thick thermal oxide). The wires hav
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