A Parallel Algorithm for Solving a Partial Eigenvalue Problem for Block-Diagonal Bordered Matrices

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A PARALLEL ALGORITHM FOR SOLVING A PARTIAL EIGENVALUE PROBLEM FOR BLOCK-DIAGONAL BORDERED MATRICES O. M. Khimich,1† O. V. Popov,1‡ O. V. Chistyakov,1†† and V. A. Sidoruk1‡‡

UDC 519.6

Abstract. A hybrid algorithm of the iterative method for the solution subspace of a partial generalized eigenvalue problem for symmetric positive definite sparse matrices of block-diagonal structure with bordering on hybrid computers with graphic processors is proposed, efficiency coefficients of the algorithm are obtained, and the algorithm is tested against test and practical problems. Keywords: algebraic eigenvalue problem, computer of hybrid architecture, hybrid algorithm, subspace iterative method, efficiency of parallel algorithm, small-tiled algorithm. INTRODUCTION Mathematical modeling of various objects in science and technology, in socio-economic processes, as well as in natural phenomena is reduced in many cases to solving an algebraic eigenvalue problem (AEVP) [1]. At the same time, the desire to obtain more reliable results for computational problems necessitates of solving an AEVP for matrices of large orders. (At the present time, problems with a matrix order of several tens of millions are widespread.) In most cases, when discretizing boundary-value problems by the finite element method or by the method of finite differences, symmetric positive definite sparse matrices arise, whose structure is determined by the numbering of unknown problems, and it can often be striped, profile, block-diagonal with a border, etc. [2]. To effectively solve the emerging high-dimensional AEVPs, it is necessary to use modern supercomputers and create algorithms that take into consideration the specifics of matrix sparsity, as well as the architectural and technological features of computers. At the present time, such computers are supercomputers of various parallel architectures. Among them, hybrid architectures (multicore computers of MIMD architecture with coprocessors-accelerators (often graphic) of SIMD-architecture [3]) are particularly promising. FEATURES OF HYBRID COMPUTERS AND SOFTWARE LIBRARIES FOR THEM When creating efficient hybrid algorithms for MIMD computers with graphic processors, it is necessary to take into consideration the peculiarities of their complex architecture. In what follows, a hybrid computer is considered, whose architecture consists of a multi-core MIMD computer (CPU) with a communication topology between hypercube processors and graphic SIMD processors (GPU). Each of the p computing processes on CPU cores with the logical numbers i = 0, 1, 2,K interacts with one GPU processor with the same number. This architecture is often denoted as p CPU + p GPU. The CPU computing nodes are connected by a certain communication environment, and the access to the data that is located in the memory of other nodes takes a longer time. The CPU and the GPU nodes have separate memories, thus, the data that has to be manipulated on GPUs must be explicitly copied from the CPU memory to the GPU memory and 1

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