Analytical and High-Resolution TEM Characterizations for Nanoscale Fractured Interfaces in Deep-Subquarter-Micron 256MBi
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Analytical and High-Resolution TEM Characterizations for Nanoscale Fractured Interfaces in Deep-Subquarter-Micron 256MBit DRAM Devices
Wei (Wayne) ZHAO Department of Technology Transfer, Infineon Technologies Richmond 6000 Technology Blvd., Sandston, VA 23150, USA
ABSTRACT Interfaces, contacts, and homo- or hetero-junctions are critical components in nanometer dynamic random access memory (DRAM) semiconductor devices. With shrinkage in device dimensions, interfacial analysis by TEM becomes more and more challenging, especially in the case of investigating failure mechanisms for nanoscale FRACTURED INTERFACES where electronic signatures found to be open. In this article, fractured interfaces at several C1-type contacts (a path between a Bitline and a Metal 1 interconnector) in a deep-subquarter-micron 256Mbit DRAM device were investigated by a JEOL 2010F analytical transmission electron microscope (TEM) with field-emission gun (FEG) running at 200KV. Considering the difficulty to exactly focus the fractured nano-scale interfaces at sufficiently high magnifications, high-resolution TEM (HR-TEM) and analytical scanning transmission electron microscopy (STEM) coupled with x-ray energy dispersive spectroscopy (XEDS) elemental linescan techniques were employed to provide supplemental information from difference prospects. An in-depth understanding for the nanoscale interfacial fracture mechanisms was established, and a simple model is initiated accordingly.
INTRODUCTION With multiple materials incorporated into an integrated circuit (IC), e.g., single crystal Si, doped polycrystalline Si, Si3N4 spacer, Ti liner, tungsten silicide gate, and Al or Cu interconnector, a nanoscale DRAM device is basically a piece of nano-composite in eye of TEM scientists.[1] To fully understand the orientation relationships and crystallization habits among INTACT interfaces/contacts formed by these materials is already a quite sophisticated job.[1~3] However, in failure analysis for microelectronics, the true headache to a TEM scientist is to analyze FRACTURED INTERFACES of these contacts at nano-to atomic-scale. Up to date, there is no literature regarding TEM fractography analyses, let alone TEM fractographic studies at nanoscales. Unfortunately, contact fails are frequent and inevitable for nanometer complex semiconductor devices during massive productions, where different materials have experienced many thermal and stress cycles during and post fabrications, such as annealing, chemical and mechanical planarization (CMP), and backend burning-in test, e.g., accelerated
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tests in extreme conditions of temperature, humidity, stress, and bias.[4~10] This article is targeted to address TEM investigations of FRACTURED nanoscale interfaces, using failures related to C1-type contacts as an example.
EXPERIMENTS Typical failed sites on DRAM chips were identified and cleaved from 200 mm DRAM wafers and/or components/modules fabricated by Infineon Technologies Richmond site. The C1 contacts and the Bitline were deposited with st
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