Clocking
FPGAs are designed to be used with synchronous design techniques. As such, understanding clocking structures and their capabilities is vital to be able to realize a design. Poor understanding will create designs that are unreliable and difficult to meet t
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Clocking John Blaine
12.1
Clocking in FPGA Designs
FPGAs are designed to be used with synchronous design techniques. As such, understanding clocking structures and their capabilities is vital to be able to realize a design. Poor understanding will create designs that are unreliable and difficult to meet timing, while good understanding will create reliable designs and allow you to focus on resolving non-clocking issues. FPGA clocking is not a difficult subject to understand. Wherever you face a design decision, opt to prioritize clocking and keep the clocking as simple as possible. This simple rule will guide you well. Often decisions taken that do not give optimal clocking performance will result in delays to the project, board respins, etc. FPGAs provide low skew clock routing. These are high load distribution networks. The network is fully buffered by design. It does not reduce in performance as you increase the load. One key progression in UltraScale FPGAs is to provide more clocking flexibility when compared to older FPGAs. There are many more available networks to use now. Additionally, FPGAs provide PLLs/MMCMs that allow you to do frequency synthesis and phase shifting. These attributes allow you to interface to external components and generate internal clocks of almost any frequency up to the maximum operating range of the FPGA. This allows for efficient FPGA design as you can easily change the frequency at which the design operates to be optimal for the given FPGA and part of the design.
J. Blaine (*) Xilinx, London, UK e-mail: [email protected] © Springer International Publishing Switzerland 2017 S. Churiwala (ed.), Designing with Xilinx® FPGAs, DOI 10.1007/978-3-319-42438-5_12
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J. Blaine
12.2
Choice of Clock Frequency
A typical FPGA design has many clock networks, as shown in Fig. 12.1, because each of the following may have its own network: • • • •
Each source synchronous interface coming into or leaving the FPGA Each transceiver interface Internal system FPGA clock network Low-speed clocking networks for control like high fanout processor control via an AXI-Lite interface, external flash clocking • Optional internal fast clock networks for conducting DSP operations Most designs do not run at any single clock frequency. Design frequencies are normally dictated by: • Bandwidth of incoming data • Bandwidth of outgoing data • Resource consumed by a particular function
The first two points are typically decided by the system. However, the third point is a design decision, in the sense that there might be multiple combinations of freq vs. utilization that would be possible. Generating different frequency clocks is easy in a FPGA. Running something faster will usually save resource. So, you can change frequency to save FPGA resource like DSP slices. Ultrascale FPGA SRC_SYNC_CLK
FWD_CLK
S O U R C E S Y N C I / F
FREQ CHANGE F I F O
SYS_CLK
HIGH PERFORMANCE DSP
HIGH PERFORMANCE DSP CONTROL SYSTEM SYNCHRONOUS I/F AXI_CLK
Fig. 12.1 A high level look at a typical clock network
F I
