Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers
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0970-Y04-02
Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers Ronald J. Gutmann, J. Jay McMahon, and Jian-Qiang Lu Center for Integrated Electronics, Rensselaer Polytechnic Institute, CII 6015, 110 8th St, Troy, NY, 12180 ABSTRACT A monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 µm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.
INTRODUCTION Wafer-level three-dimensional (3D) integration with through-wafer, micron-size vias offers low interconnect delay and power dissipation for advanced digital ICs such as multicore processors, as well as low interconnect parasitics in a monolithic technology platform for high-packing density heterogeneous integration. Most of the technology platforms have focused on extending the integrated circuit (IC) back-end-of-the-line (BEOL), to include wafer-to-wafer alignment, wafer bonding, wafer thinning and inter-wafer interconnect processing. This manuscript describes a monolithic wafer-level 3D technology platform which is compatible with wafer-level packaging (WLP) technology and provides a high-packing density, 3D heterogeneous integration capability with low-parasitic, micron-sized inter-die vias. This technology platform incorporates damascene-patterned copper-benzocyclobutene (Cu-BCB) redistribution layers in a via-first process flow. Figure 1 depicts two 3D technology platforms that have been examined extensively, namely a via-first Cu-Cu bonding platform [1-3] and a vialast BCB-BCB bonding platform [4-6]. The via-first Cu-Cu platform offers high density of inter-wafer vias with one unit process for both wafer bonding and inter-wafer electrical via formation [7-10]. The via-last BCB-BCB platform has two key advantages: surface nonplanarity is easily tolerated by the spin-on BCB and the adhesive bonding strength is significantly higher. A similar technology, without the micron-sized via capability, has been used for microelectromechanical systems (MEMS) and smart sensors [11-12].
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