Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions
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https://doi.org/10.1007/s11664-020-08353-x Ó 2020 The Minerals, Metals & Materials Society
TOPICAL COLLECTION: U.S. WORKSHOP ON PHYSICS AND CHEMISTRY OF II-VI MATERIALS 2019
Dislocation Sidewall Gettering in II-VI Semiconductors and the Effect of Dislocation Pinning Interactions T. KUJOFSA
1,2,3
and J.E. AYERS1
1.—Electrical and Computer Engineering Department, University of Storrs, CT 06269-4157, USA. 2.—e-mail: [email protected]. [email protected]
Connecticut, 3.—e-mail:
It has been shown that threading dislocations may be removed from patterned mismatched heteroepitaxial layers through a process of dislocation sidewall gettering (DSG), also known as patterned heteroepitaxial processing (PHeP). This gettering approach involves the glide of dislocations toward sidewalls, where they become trapped by image forces. Simple quantitative models have been developed for DSG, but they fail to explain why only partial removal of dislocations was observed in ZnSSe/GaAs (001) whereas complete removal has been achieved in ZnSe/GaAs (001) with higher lattice mismatch. Until now this phenomenon has been qualitatively explained by the presence of sessile dislocations. Here we present a quantitative model for pinning interactions and show that these interactions can limit the growth of misfit dislocation segments and thereby reduce the effectiveness of DSG in ZnSySe1-y/GaAs (001) relative to ZnSe/GaAs (001). Key words: Dislocation gettering, plastic flow model, dislocation flow, pinning
INTRODUCTION An important defect engineering approach for the removal of threading dislocations from metamorphic semiconductor device structures is patterned heteroepitaxial processing (PHeP),1–7 also known as dislocation sidewall gettering (DSG). This approach involves patterned growth or planar growth followed by patterning and annealing. During growth or annealing of the patterned heteroepitaxial material, dislocations may be gettered by sidewalls due to the attractive image force of the free surface, provided that dislocations may glide to produce a length of misfit dislocation equal to at least one-half of the mesa width. In the case of ZnSe/GaAs (001) heterostructures, complete removal of threading dislocations was achieved by the annealing (30 min, 600°C) of 70-lm-wide square mesas with
(Received February 8, 2020; accepted July 23, 2020)
a layer thickness of 0.6 lm.3 However, in the case of ZnS0.02Se0.98/GaAs (001) heteroepitaxial layers, complete removal of threading dislocations was not achieved using the same geometry, anneal time, and anneal temperature.7 This behavior, though not completely understood, has been generally attributed to the presence of sessile dislocations. Despite this, DSG has been widely applied to II-VI infrared detector focal plane arrays and III-V light-emitting diodes used in flat-panel displays. These applications have been guided by empirical development rather than predictive models, and it is therefore of great interest to refine the quantitative models for DSG. The goal of the present work
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