Do You Really Expect To Grow Epilayers On That? A Rationale For Growing Epilayers On Roughened Surfaces
- PDF / 247,553 Bytes
- 8 Pages / 612 x 792 pts (letter) Page_size
- 40 Downloads / 203 Views
0911-B03-06
Do You Really Expect To Grow Epilayers On That? A Rationale For Growing Epilayers On Roughened Surfaces J. J. Sumakeris1, Brett A. Hull1, Michael J. O'Loughlin1, S. Ha2, Marek Skowronski2, John W. Palmour1, and Calvin H. Carter, Jr. 1 1 Cree, Inc., 4600 Silicon Dr., Durham, NC, 27703 2 Materials Science and Engineering, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, PA, 15213
ABSTRACT We describe surface preparation and epilayer growth techniques that readily reduce the density of Vf drift inducing basal plane dislocations in epilayers to less than 10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The optimal process route requires etching the substrate surface prior to epilayer growth to enhance the natural conversion of basal plane dislocations into threading edge dislocations during epilayer growth. The surface of this relatively rough “conversion” epilayer is subsequently repolished prior to growing the device structure. We provide details on processing parameters and potential problems as well as describe devices produced using this low basal plane dislocation growth processes. INTRODUCTION The unprecedented performance of bipolar SiC based power devices can dramatically improve the efficiency and capability of power control systems. However, the advancement of this class of device has been stymied in recent years due to forward voltage instability (Vf drift) brought on by the expansion of structural defects within many of the devices during operation. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into conduction limiting Shockley stacking faults within device regions that experience conductivity modulation [1-3]. This widespread recognition has led to the development of several approaches to stabilize or eliminate stacking faults or the nucleating dislocations. The use of thick buffer layers to retain minority carriers from the substrate or ohmic contacts is one helpful approach; as is the continuous epitaxial growth of all portions of a device that experience modulation to avoid the reintroduction of BPDs observed at growth interruptions [4]. In addition, a superior surface finish coupled with hydrogen etching prior to epilayer growth has been found to suppress the propagation of substrate dislocations into epilayers, especially for C-face growth [5]. More recently, a selective etch, with a reagent such as molten KOH, prior to epilayer growth has been reported to be the most effective means of reducing the BPD density in epilayers [6-8]. Although one can very effectively convert substrate BPDs into more benign threading edge dislocations (TEDs) in an epilayer grown on an etched surface, the roughened surface can lead to difficulties in subsequent processing. For example, overall defect densities can be abnormally high and lithography becomes more difficult on rougher surfaces. Repolishing this “conversion” epilayer’s surface before growing the device epi l
Data Loading...
