Enhanced Loop Coalescing: A Compiler Technique for Transforming Non-uniform Iteration Spaces
Parallel nested loops are the largest potential source of parallelism in numerical and scientific applications. Therefore, executing parallel loops with low run-time overhead is very important for achieving high performance on parallel computers. Guided s
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Editorial Board David Hutchison Lancaster University, UK Takeo Kanade Carnegie Mellon University, Pittsburgh, PA, USA Josef Kittler University of Surrey, Guildford, UK Jon M. Kleinberg Cornell University, Ithaca, NY, USA Alfred Kobsa University of California, Irvine, CA, USA Friedemann Mattern ETH Zurich, Switzerland John C. Mitchell Stanford University, CA, USA Moni Naor Weizmann Institute of Science, Rehovot, Israel Oscar Nierstrasz University of Bern, Switzerland C. Pandu Rangan Indian Institute of Technology, Madras, India Bernhard Steffen University of Dortmund, Germany Madhu Sudan Massachusetts Institute of Technology, MA, USA Demetri Terzopoulos University of California, Los Angeles, CA, USA Doug Tygar University of California, Berkeley, CA, USA Gerhard Weikum Max-Planck Institute of Computer Science, Saarbruecken, Germany
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Jesús Labarta Kazuki Joe Toshinori Sato (Eds.)
High-Performance Computing 6th International Symposium, ISHPC 2005 Nara, Japan, September 7-9, 2005 and First International Workshop on Advanced Low Power Systems, ALPS 2006 Revised Selected Papers
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Volume Editors Jesús Labarta Universidad Politecnica de Catalunya Spain E-mail: [email protected] Kazuki Joe Nara Women’s University Japan E-mail: [email protected] Toshinori Sato Kyushu University Japan E-mail: [email protected]
Library of Congress Control Number: 2007943157 CR Subject Classification (1998): D.1, D.2, F.2, E.4, G.1-4, J.1-2, J.6, I.6 LNCS Sublibrary: SL 1 – Theoretical Computer Science and General Issues ISSN ISBN-10 ISBN-13
0302-9743 3-540-77703-2 Springer Berlin Heidelberg New York 978-3-540-77703-8 Springer Berlin Heidelberg New York
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Preface
This is the joint post-proceedings of the 6th International Symposium on High Performance Computing (ISHPC-VI) and the First International Workshop on Advanced Low Power Systems 2006 (ALPS2006). The post-proceedings also contain the papers presented at the Second HPF International Workshop: Experiences and Progress (HiWEP2005) and the Workshop on Applications for PetaFLOPS Computing (APC2005), which are workshops of ISHPC-VI. ISHPC-VI, HiWEP2005 and APC2005 were held in Nara, Japan during September 7–9, 2
