EUV Lithography: Patterning to the End of the Road
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EUV Lithography: Patterning to the End of the Road Jonathan L. Cobb,1 Robert L. Brainard,2 Donna J. O'Connell,3 and Paul M. Dentinger3 1 Motorola DigitalDNA Laboratories, Austin, TX 78721 2 Shipley Company, 455 Forest St., Marlborough, MA 01752 3 Sandia National Laboratory, Livermore, CA 94551 ABSTRACT Extreme Ultraviolet (EUV) lithography is gaining momentum as the patterning technology of choice for the semiconductor nodes with less than 70-nm half-pitch. As such, it must be ready for manufacturing in the 2006-2007 time frame, and it must be extendable to the lower limits of CMOS technology. Successful patterning of 40-nm dense lines in viable EUV photoresists indicates that today's resist materials may have the necessary resolution, but better optics are needed to verify this more rigorously. Although little is understood about the impact of lineedge roughness (LER) on device performance, it is generally assumed that EUV LER must be less than 3 nm 3σ. EUV lines have been printed with LER as low as 4 nm 3σ, but they were printed with unacceptable photospeed. Deliberate attempts to increase the photospeed while maintaining low LER have produced a resist with sizing dose of 1.7 mJ/cm2 and LER of 6.6 nm 3σ. Photospeed is important because EUV photons are difficult to create, and the photoresist must use them efficiently for economically acceptable throughput. Throughput models indicate that patterning doses may need to be 1-2 mJ/cm2, and only 30-40% of these photons will be absorbed, so the resists must be able to accommodate statistical dose fluctuations that are an appreciable fraction of the mean dose. Highly sensitive resists such as these have been produced with good LER. Since all resist materials absorb EUV radiation strongly, the photoresist layer will have to be less than 150 nm thick. Resists this thin pose problems for device manufacturing, largely because they will not have acceptable etch resistance, and this etch resistance will have to be recovered in some other way. Efforts have begun to integrate hard masks with thin resists in real device fabrication. Defect data indicate that defect densities do not increase in resist films less than 100 nm thick, and transistors, via chains, and microprocessors have all been fabricated with these thin-resist/hard-mask integrations. INTRODUCTION Extreme Ultraviolet (EUV) lithography is scheduled to be inserted into large-volume integrated circuit manufacturing in 2006-2007 at a half-pitch below 70 nm. An attractive feature of the lithography technology is its short wavelength (13-14 nm) which suggests that it can be extended to the limits of CMOS device scalability. Although EUV lithography will continue the historical use of photon-based exposure, the technology differs significantly from the optical tools in use today. For instance, the demanding source, multilayer coating, mask fabrication, and vacuum environment technologies which must be employed have received significant attention in the literature [1]. In addition to the different source, mask, and optics te
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