Extraction of performance parameters of nanoscale SOI LDD-FinFET using a semi-analytical model of capacitance and channe
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Extraction of performance parameters of nanoscale SOI LDD‑FinFET using a semi‑analytical model of capacitance and channel potential for low‑power applications Ankit Dixit1 · Dip Prakash Samajdar1 Received: 14 May 2020 / Accepted: 1 September 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract In this paper, we have investigated the performance of a silicon-based low-doped drain (LDD) SOI-FinFET for the first time and compared it with conventional FinFET for implementation in logic circuits. It is well known that the use of the conventional LDD technology in the triple gate FinFETs reduces the electric field near the drain region and hot carrier effect at the cost of reduced current driving capability as is reported in LDD MOSFETs. We observe a reduction in the peak electric field by 15% near the drain region with a subsequent degradation in the electron velocity, as well. We have presented a semianalytical approach to model the gate capacitance, drain current, channel potential, and subthreshold slope for the proposed FinFET structure. 3D simulation results for three different channel lengths using the TCAD Sentaurus tool are used to validate the computed results. DC analysis of the LDD-FinFET is performed and results are compared with the conventional FinFET device in terms of threshold voltage, transconductance, and ION ∕IOFF ratio. The capacitance model is used to investigate the subthreshold swing and current driving capability of the proposed device. In addition to this, circuit-level analysis like voltage transfer characteristics and switching characteristic of proposed CMOS inverter using SOI LDD-FinFET is performed. The results presented in this paper can be utilized for the design of low-power digital applications to cater to the requirements of high switching speeds, high gain, and minimum power dissipation. Keywords CV curve · CMOS inverter · Device modeling · Gate capacitance · Hot carrier effect · VTC curve · Trigate FinFET
1 Introduction The continuous downsizing of the planar MOSFETs to keep pace with Moore’s law caused serious degradation in the device performance, thereby retarding the development of Si-based CMOS technology [1, 2]. The sub-micron transistors are prone to short-channel effects (SCEs) owing to their narrow channel lengths as a result of which the gate loses its controllability over the channel [3]. In the last few decades, novel multi gate (MG) FETs have emerged as strong alternatives to its planar counterpart in terms of short-channel * Dip Prakash Samajdar [email protected] Ankit Dixit [email protected] 1
PDPM Indian Institute of Information Technology, Design and Manufacturing, Jabalpur, India
performance metrics such as subthreshold swing (S), drain induced barrier lowering (DIBL), hot carrier effect, drain punch through, and threshold voltage ( Vth ) roll off. The short-channel effect in sub-micron devices are controlled by specific fabrication process like halo implant [4], reverse halo implant [5], LDD, etc. Among all the multi-gate fi
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