FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing
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FPGA-Based Configurable Systolic Architecture for Window-Based Image Processing ´ Cesar Torres-Huitzil Computer Science Department, National Institute for Astrophysics, Optics and Electronics, P.O. Box 51 and 216, 72000 Puebla, Mexico Email: [email protected]
Miguel Arias-Estrada Computer Science Department, National Institute for Astrophysics, Optics and Electronics, P.O. Box 51 and 216, 72000 Puebla, Mexico Email: [email protected] Received 13 September 2003; Revised 21 May 2004 Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A fieldprogrammable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of 7 × 7 configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to 7 × 7, but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of 3.16 GOPs at a 60 MHz clock frequency and a processing time of 8.35 milliseconds for 7 × 7 generic window-based operators on 512 × 512 gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness. Keywords and phrases: FPGA, configurable system, real time, window-based image processing, systolic array.
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INTRODUCTION
Designing a hardware processor core for data-intensive image processing is a fundamental step in developing modern machine vision systems that can efficiently implement computer vision related tasks. The wide interest in dataintensive or window-based image processing is due to the fact that more complex algorithms use the low-level results as primitives to pursue higher-level goals [1]. However, building such systems remains difficult because of three main reasons [2]. First, most computer vision applications are computational intensive tasks difficult to overcome using conventional processors. The sequential nature of conventional processors and the huge amount of redundant data involved in an image slow down the performance of vision systems. Second, heterogeneity of computations in the processing performed through an application limits the parallelization. A mismatch, therefore, exists between the complexity of the required operations and the processing power offered by processors. Third, several vision applications require systems with real-time performance. A real-time system is one that must interact with its environment under responsetime constraints [3, 4]. Real-time image processing systems
interact with their environment, and thus they must produce outputs that are not only numerically correct, but which also meet timing constraints necessary for these interactions. On th
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