General Overview of Pipeline Analog-to-Digital Converters
This chapter provides a general background for the work carried out in this book. Therefore, its purpose is to cover all aspects of the developed work. First, some A/D converter (ADC) architectures will be briefly described. The common element of these ar
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General Overview of Pipeline Analog-to-Digital Converters
Abstract This chapter provides a general background for the work carried out in this book. Therefore, its purpose is to cover all aspects of the developed work. First, some A/D converter (ADC) architectures will be briefly described. The common element of these architectures is the use of the multiplying-DAC (MDAC) circuit as their principal block. Advantages and limitations of the architectures will also be given. The MDAC circuit is one of the key elements of this book. Given that this work presents a prototype of a pipeline ADC, it is important to describe each of its building blocks. Besides detailing the function and importance of each block, related errors and performance limiting aspects will also be given. After the description of the pipeline converter sub-blocks, various static and dynamic performance parameters, and metrics that characterise ADCs are given. It will be the objective here to explain the parameters that fundamentally dictate the performance of ADCs. Finally, the chapter is completed with a state-of-the-art of medium-low resolution high-speed pipeline ADCs. Besides this overview, surveys of two key building blocks, namely, two-stage amplifiers and reference voltage circuits (in the context of A/D conversion), which deserved special attention in this work, are also presented.
2.1 MDAC-Based Analog-to-Digital Converter Architectures There are many architectures of A/D converters, each with their own set of characteristics and capabilities to be used in different applications. Well known architectures are Full-Flash (or Parallel), Two-Step, Sub-Ranging, Folding, Integrating, Successive Approximation (SA), Algorithmic, Pipeline, Sigma-Delta modulators, and Time-toDigital. It is also possible to find numerous combinations of the various existing topologies, such as: time-interleaving can be used as a means of increasing the sampling frequency (conversion rate) by arranging various converters of the same type in parallel; it is very frequent to find interpolation associated with flash and folding converters; the two-step topology can employ either flash or SA architecture in each
M. Figueiredo et al., Reference-Free CMOS Pipeline Analog-to-Digital Converters, Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-3467-2_2, © Springer Science+Business Media New York 2013
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2 General Overview of Pipeline Analog-to-Digital Converters
step; the pipeline and algorithmic topologies usually employ flash converters in each step, etc. Part of the work carried out in this book implements an ADC topology that employs MDAC circuits, consequently, the only converter topologies of interest, of the ones mentioned above, are those that use MDAC circuits as a means of obtaining a residue with amplification (i.e., simultaneous DAC, subtraction, and residue amplification functions). With this in mind the only architectures that will be discussed are the Two-Step (flash), the multi-step Algorithmic, and the Pipeline, targeting higher conversi
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