Location of Current Carrying Faults in Integrated Circuits by Magnetic Force Microscopy
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Location of Current Carrying Faults in Integrated Circuits by Magnetic Force Microscopy A.Pu, A. Rahman, D.J. Thomson, and G.E. Bridges Department of Electrical and Computer Engineering, University of Manitoba Winnipeg, Manitoba, Canada R3T 5V6
Abstract In Integrated Circuits failure analysis excessive power supply current flowing into the IC is often used to indicate the presence of a faulty device. Location of these faulty devices can be problematic as the devices are often buried under several layers of conducting interconnect. By imaging the magnetic field produced by current flowing in an IC a faulty device can be located. In this paper we present experimental results on imaging current-carrying faults on integrated circuits using Magnetic force microscopy. We have experimentally determined that MFM is capable of measuring currents as small as 1 to 10 microampere on ICs in a 30 Hz bandwidth. We have carried out modeling calculations comparing the simulation results with experimental results using realistic MFM tip geometry. From these results we have devised a method to accurately locate the position of the internal current carrying faults from MFM images with micrometer uncertainty. Key words: MFM; Fault location; Failure Analysis. 1. INTRODUCTION In recent years magnetic force microscopy (MFM)[1,2] has proven to be a useful tool for studying microscopic magnetic systems as it directly images the stray field distribution above the surface of a magnetic sample on a nanometer scale without extensive sample preparation. MFM, an offshoot of atomic force microscopy [3], uses a sharp magnetic tip mounted at the end of a micro-machined cantilever raster scanned over the surface of sample at small distances. The magnetic interaction of the tip with the stray field emanating from the sample causes the deflection of the cantilever. The deflection is detected by a high-sensitivity deflection sensor, often a laser beam-bounce sensor [4]. Since the original MFM work by Martin and Wickramasinghe [5], a number of experimental and theoretical works have been reported, including high resolution imaging of various domain wall structures [6,7] and writing recording media [8], quantifying MFM images [9], MFM-image simulation[10], and micromagnetic modeling of MFM tips [11]. However, relatively few works have dealt with the application of MFM to Integrated Circuits (IC) failure analysis [12]. In this article we present results on imaging current-carrying lines and simulated faults on integrated circuits (IC) using MFM. We present a comprehensive study and give the measurement sensitivity of the MFM system. In particular, we have modeled the field generated by faulty devices which exists between power and ground lines in a typical IC geometry. We have calculated the forces generated for realistic MFM tip geometries and from this have devised a method to accurately locate the position of current carrying faults from MFM images. 2. EXPERIMENTAL TECHNIQUE The technique we are proposing in this paper would be applicable to fa
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