Low-voltage reduced complexity cells for MOS translinear loops
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Low-voltage reduced complexity cells for MOS translinear loops C. Psychalinos · C. Laoudias
Received: 31 August 2012 / Revised: 6 February 2013 © Springer Science+Business Media New York 2013
Abstract A novel bias scheme for realizing low-voltage second-order translinear loops is introduced in this paper. The provided design examples include current geometric-mean, squarer/divider, and multiplier/divider cells. The performed comparison shows that the derived analog signal processing blocks offer reduced circuit complexity and improved performance, compared with the corresponding already published counterparts. Keywords CMOS analog integrated circuits · Low-voltage circuits · Non-linear signal processing · MOS translinear loop · Current-mode multiplier/divider 1 Introduction The MOS translinear principle (MTL) is applicable in an even number of MOS transistors arranged in a closed loop, in such a way that the sum of their gate-source voltages is equal to zero [5]. A suitable loop topology towards the realization of lowvoltage analog processing systems is the up-down (or alternate) loop. Based on that general scheme, a number of current geometric-mean circuits, with MOS transistors in saturation region, have been already proposed in the literature [1, 2, 4]. The bias of the loop has been performed by employing the Flipped Voltage Follower (FVF) [1, 4] or floating voltage sources [2]. All the aforementioned topologies have a minimum supply voltage requirement equal to VTH + 2VDS,sat , where VTH is the threshold voltage, and VDS,sat is the drain-source saturation voltage of a MOS transistor. A comparative study performed in [3] show that biasing the translinear loop using the FVF cell C. Psychalinos () · C. Laoudias Electronics Laboratory, Physics Department, University of Patras, 26504, Rio Patras, Greece e-mail: [email protected] C. Laoudias e-mail: [email protected]
Circuits Syst Signal Process
[1, 4] leads to realizations with improved performance, in terms of circuit complexity and bandwidth. A novel bias scheme for second-order translinear loops, based on the employment of FVFs, is introduced in this paper. Current geometric mean, squarer/divider, and multiplier/divider blocks are derived as design examples, and their performance have been evaluated by employing the Analog Design Environment of Cadence software. The obtained comparison results show that the proposed cells offer a significant reduction of circuit complexity, power dissipation and, also, improved bandwidth and linear performance with regards to the corresponding already published structure. All these achievements have been done without increasing the minimum supply voltage requirement. The paper is organized as follows: the proposed biasing scheme is presented in Sect. 2. Some important analog processing blocks are given in Sect. 3, while their performance has been evaluated and compared with those of the corresponding already published cells in Sect. 4.
2 Proposed bias scheme The core of the bias scheme for a second-order trans
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