Magnetic Domain Wall Race Track Memory
During the past four decades, semiconductor industry has witnessed a race between the development of processing devices/systems and memory technologies following the Moore’s law. With the end of Moore’s era on the silicon roadmap, the processing technolog
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Magnetic Domain Wall Race Track Memory
5.1
Introduction
During the past four decades, semiconductor industry has witnessed a race between the development of processing devices/systems and memory technologies following the Moore’s law. With the end of Moore’s era on the silicon roadmap, the processing technologies are apparent frontrunner than the memory counterparts in terms of accessing speed and integration volumes [1]. In fact, the failure of prevailing memory technologies to cope up with the speed of the modern processors have pressed the researchers to discover new technologies to meet the requirements of the present and futuristic ultra-high speed communication and data processing applications. As discussed in Chap. 1, the pyramidal shape of the modern memory hierarchy has become the major bottleneck for the integration of high-speed processors and ultra-high density fast memory technologies on the same silicon chip. At the bottom of the memory hierarchy, the hard-disk drives (HDDs) are with the highest density in terabytes (TB), however, exhibit very sluggish access time in milliseconds and possess the size which is totally unfit for the on-chip integration. To achieve higher speed, existing memory technologies such as SRAMs and DRAMs have to trade-off with the capacity. At the highest level of the memory hierarchy SRAMs exhibit the highest access speed of around 1 ns and capability of on-chip integration with the high-end processors; however, the capacities of these embedded memories are still in the range of kilobytes (KB), which is insufficient for the modern day processors. These high-speed embedded memories are volatile in nature; hence, the retention of the data after power failure or during the OFF mode is the major problem. Furthermore, the contemporary computing system on single board still utilizes different memory technologies, right from HDD to SRAMs, at different architecture levels; which increases the complexity and cost of the systems with lesser efficiency. Hence, a non-volatile memory (NVM) technology with capability of ultra
© The Author(s) 2017 B.K. Kaushik et al., Next Generation Spin Torque Memories, SpringerBriefs in Applied Sciences and Technology, DOI 10.1007/978-981-10-2720-8_5
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high density storage, very low access time, and on-chip integration is the need of the hour for the nanocomputing industry [2].
5.1.1
Limitations of Existing and Emerging Memory Technologies
As the computing industry experiences the pressing requirement of replacing the pyramidal memory hierarchy with a non-volatile on-chip high speed magnetic memory technology, it is appropriate to figure out the constraints of the existing and emerging memory technologies. The hard-disk drives evolved in 1950s, and remained the part of the computing systems as a main memory till today due to its non-volatility and capability of storing huge data required for the current high-end applications. The HDDs offer a least cost-per-bit with the TB storage capacity. However, wit
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