Memristive response of a new class of hydrated vanadium oxide intercalation compounds
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Research Letter
Memristive response of a new class of hydrated vanadium oxide intercalation compounds Justin L. Andrews, Department of Chemistry, Texas A&M University, College Station, TX 77843, USA; Department of Materials Science and Engineering, Texas A&M University, College Station, TX 77843, USA Sujay Singh and Colin Kilcoyne, Department of Physics, University at Buffalo, State University of New York, 239 Fronczak Hall, Buffalo, NY 14260, USA Patrick J. Shamberger, Department of Materials Science and Engineering, Texas A&M University, College Station, TX 77843, USA G. Sambandamurthy, Department of Physics, University at Buffalo, State University of New York, 239 Fronczak Hall, Buffalo, NY 14260, USA Sarbajit Banerjee, Department of Chemistry, Texas A&M University, College Station, TX 77843, USA; Department of Materials Science and Engineering, Texas A&M University, College Station, TX 77843, USA Address all correspondence to G. Sambandamurthy, Sarbajit Banerjee at [email protected], [email protected] (Received 19 June 2017; accepted 26 July 2017)
Abstract The practical realization of energy-efficient computing vectors is imperative to address the break-down in the scaling of power consumption with transistor dimensions, which has led to substantial underutilized chip space. Memristive elements that encode information in multiple internal states and reflect the dynamical evolution of these states are a promising alternative. Herein we report the observation of pinched loop hysteretic type-II memristive behavior in single-crystalline nanowires of a versatile class of layered vanadium oxide bronzes with the composition δ-[M(H2O)4]0.25V2O5 (M = Co, Ni, Zn), the origin of which is thought to be the diffusion of protons in the interlayer regions.
Introduction In recent process generations, the Dennard scaling of power consumption with transistor dimensions has been interrupted, resulting in stagnation of clock frequencies and giving rise to a fundamental utilization wall.[1] As a result, much of the benefits derived from aggressively scaled feature densities are squandered in current computing architectures. In practical terms, this break-down in synergy between scaling of transistor density and native transistor speed on the one hand and transistor power consumption on the other hand is mitigated by leaving a substantial fraction of valuable chip real estate underclocked, engendering the term, “dark silicon”.[2] “Dark silicon” is, in fact, a casualty of the metal–oxide–semiconductor field-effect transistor paradigm (MOSFET), which is fundamentally constrained by the immutable thermodynamics of electric field-modulated switching of Si devices from OFF to ON states. Circumnavigating these fundamental limits requires either the development of new classes of materials that exploit novel resistance switching mechanisms not subject to the fundamental limitations of conventional FETs,[3] or alternatively the development of a computing architecture that encodes complexity through highly parallelized operations, similar to
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