Multichannel Baseband Processor for Wideband CDMA
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Multichannel Baseband Processor for Wideband CDMA Louay M. A. Jalloul Infineon Technologies, 1730 North First Street, San Jose, CA 95112, USA Email: [email protected]
Jim Lin Infineon Technologies, 1730 North First Street, San Jose, CA 95112, USA Email: [email protected] Received 12 March 2004; Revised 1 December 2004 The system architecture of the cellular base station modem engine (CBME) is described. The CBME is a single-chip multichannel transceiver capable of processing and demodulating signals from multiple users simultaneously. It is optimized to process different classes of code-division multiple-access (CDMA) signals. The paper will show that through key functional system partitioning, tightly coupled small digital signal processing cores, and time-sliced reuse architecture, CBME is able to achieve a high degree of algorithmic flexibility while maintaining efficiency. The paper will also highlight the implementation and verification aspects of the CBME chip design. In this paper, wideband CDMA is used as an example to demonstrate the architecture concept. Keywords and phrases: CDMA, chip-rate processing, symbol-rate processing, micro-DSP, multipath, RAKE.
1.
INTRODUCTION
Code-division multiple access (CDMA) is the physical layer access method used in third-generation (3G) mobile radio systems [1]. 3G systems have improved receiver performance over any of the current cellular systems due to the introduction of several new physical layer techniques such as coherent demodulation [2] and turbo codes [3], just to name a few. Relative to the second-generation (2G) standards [4], 3G systems are also designed for both voice and high-speed data. The wideband CDMA 3G technology uses larger bandwidth and a higher chip-rate than the 2G CDMA counterpart [4]. Furthermore, 3G standards are evolving to support additional features such high-speed downlink packet access, enhanced uplink dedicated channel and multiple-input multiple-output antenna technology. 3G transceiver solutions must also have a rapidly decreasing cost per channel as a function of time. These features present a serious challenge in the efficient design and implementation of 3G transceiver solutions. There are two typical approaches for development of baseband solutions to handle the above-mentioned design features. The first is a dedicated implementation, such as an application-specific integrated circuit (ASIC). The second implementation is a programmable architecture, such as a general purpose central processing unit (CPU) or fieldprogrammable gate arrays (FPGA). ASIC solutions continue to be the technology of choice for high-volume production
due to their efficiency, measured in terms of MOPS/mW, but they do not provide the required algorithmic flexibility. Finetuning the algorithms’ performance delays the chip tapeout which typically results in a large cost. On the other hand, the FPGA approach offers a high degree of flexibility that makes them highly suitable for prototyping, but lacks the energy/power efficiency. FPGA implementations are also cost
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