Optimization of Deposition Thickness and Over Polishing Time to Minimize Wafer Level Topography in Copper CMP
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Optimization of Deposition Thickness and Over Polishing Time to Minimize Wafer Level Topography in Copper CMP J.M. Kang, Shaoyu Wu, T. Selvaraj, Benfu Lin, P.D. Foo Institute of Microelectronics, 11 Science Park Road, Singapore ABSTRACT Topography after Cu CMP is one of the main issues in constructing reliable Cu interconnects. The wafer level topography is greatly influenced by many polishing properties such as removal non-uniformity and planarization efficiency, and also by many polishing variables. Among the variables, Cu deposition thickness and over polishing time are easily controllable, and closely related to the topography. For a given polishing condition, the topography can be minimized through the optimization of Cu deposition thickness and over polishing time. A model is proposed to account for the correlation between these variables and the wafer level topography. Numerical result of this model shows a strong dependency of optimized Cu deposition thickness and over polishing time on the removal non-uniformity, dishing susceptibility and over plated bump size.
INTRODUCTION Enormous efforts have been made to reduce the topography involved in Cu CMP as Cu interconnects are widely accepted for deep sub-micron technologies. Even with a little excessive post-CMP topography, metal lines will be faced with serious problems of bridging or thinning in the upper level. Newly announced slurries and pads, in-situ monitoring techniques, and Cu deposition method, all thus have one common goal: reduce topography. For given equipment and consumable performances, wafer level topography, expressed as total-indicated-range (TIR) in this work, can be still reduced by optimizing Cu deposition thickness and over polishing time. These variables are easily controllable, but strongly correlated with each other, which makes it quite time- and material-consuming to optimize these variables experimentally for a specific pattern layout. In this work, TIR is modeled as a function of Cu deposition thickness and over polishing time. After extracting parameters for the model experimentally, numerical minimization of TIR is done to obtain optimized Cu thickness and over polishing time. The correlation between these variables and polishing properties such as removal non-uniformity and over plated bump size is discussed. EXPERIMENTAL Experiments were performed on Mirra-Mesa CMP system equipped with an end-point detection tool. Commercially available high selectivity alumina-based slurry and IC1000/SubaIV pads were used. To extract the parameters, patterned wafers with 10 to 200 µm wide and 6000 Å deep trenches and 100×100 to 500×500 µm2 square dense blocks were polished. Sematech-931 wafers were used for the parameters associated with large over-plated bumps. Just before over polishing, necessary for dishing study, CMP was switched to soft landing condition [1] where the average removal rate was 76 Å/sec. The highest dishing value on a wafer was taken and combined with the fastest removal area factor to generate parameters for dis
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