Preliminaries
This chapter provides background information on relevant and common topics for this book. First, it introduces SystemC TLM (Transaction Level Modeling), which is the language of choice to create Virtual Prototypes (VPs). Then, the main concepts of the RIS
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hanced Virtual Prototyping Featuring RISC-V Case Studies
Enhanced Virtual Prototyping
Vladimir Herdt • Daniel Große • Rolf Drechsler
Enhanced Virtual Prototyping Featuring RISC-V Case Studies
Vladimir Herdt University of Bremen and DFKI GmbH Bremen, Germany
Daniel Große Johannes Kepler University Linz Linz, Austria
Rolf Drechsler University of Bremen and DFKI GmbH Bremen, Germany
ISBN 978-3-030-54827-8 ISBN 978-3-030-54828-5 (eBook) https://doi.org/10.1007/978-3-030-54828-5 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2021 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
To Elena and Oleg, Lukas and Lothar
Preface
Virtual Prototypes (VPs) play a very important role to cope with the rising complexity in the design flow of embedded devices. A VP is essentially an executable abstract model of the entire Hardware (HW) platform and pre-dominantly created in SystemC TLM (Transaction Level Modeling). In contrast to a traditional design flow, which first builds the HW and then the Software (SW), a VP-based design flow enables parallel development of HW and SW by leveraging the VP for early SW development and as reference model for the subsequent design flow steps. However, this modern VP-based design flow still has weaknesses, in particular due to the significant manual effort involved in verification and analysis as well as modeling tasks which is both time-consuming and error-prone. This book presents several novel approaches that cover modeling, verification, and analysis aspects to strongly enhance the VP-based design flow. In addition, the book features several RISCV case studies to demonstrate th
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