Self-formation of Ti-rich Layers at Cu(Ti)/low-k Interfaces
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1079-N03-08
Self-formation of Ti-rich Layers at Cu(Ti)/low-k Interfaces Kazuyuki Kohama1, Kazuhiro Ito1, Susumu Tsukimoto1, Kenichi Mori2, Kazuyoshi Maekawa2, and Masanori Murakami1 1 Department of Materials Science and Engineering, Kyoto University, Kyoto, 606-8501, Japan 2 Process Technology Development Division, Renesas Technology Corp., Itami, 664-0005, Japan
ABSTRACT In our previous studies, thin Ti-rich diffusion barrier layers were found to be formed at the interface between Cu(Ti) films and SiO2/Si substrates after annealing at elevated temperatures. This technique was called “self-formation of the diffusion barrier,” which is attractive for fabrication of ultra-large scale integrated (ULSI) interconnects. In the present study, we investigated the applicability of this technique to Cu(Ti) alloy films which were deposited on the four low dielectric constant (low-k) dielectric layers which are potential dielectric layers of future ULSI-Si devices. The microstructures were analyzed by transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS), and correlated with the electrical properties of the Cu(Ti) films. It was concluded that the Ti-rich interface layers were formed in all the Cu(Ti)/dielectric-layer samples. The primary factor to control composition of the self-formed Ti-rich interface layers was the C concentration in the dielectric layers rather than the formation enthalpy of the Ti compounds (TiC and TiSi). Crystalline TiC was formed on the dielectric layers with a C concentration higher than 17 at.%. INTRODUCTION Although copper interconnects have been used extensively in ULSI devices for almost 10 years, there are still many materials-related issues that must be solved before Cu interconnects are used in deep sub-micron scale devices. In particular, large resistance-capacitance (RC) delay and poor device reliability are critical issues [1], and development of low dielectric interlayers and passivation materials is mandatory to reduce the RC delay [2,3]. One of the primary factors for the increase in electrical resistivity of nano-scale Cu wires is the existence of barrier layers which prevent the intermixing of Cu wires with the surrounding dielectric materials. The resistivity increases due to the barrier layers becoming significantly large with the reduction in line width of the Cu wires. Moriyama et al. [4] and Shimada et al. [5] concluded that a very thin barrier layer (< 5 nm) is required for the interconnects with a line-width of ~ 65 nm to achieve an effective interconnect resistivity of less than 4 µΩ-cm. Thus, a fabrication technique to prepare nano-scale Cu wires with ultra thin barrier layers should be developed. To prepare such thin barrier layers in Cu alloy films, new fabrication techniques to form the barrier layers by annealing at elevated temperatures were extensively studied [6-11]. This technique is conventionally called “self-formation of the barrier layer,” and application of this technique to the fabrication process of Cu interconnects is attractive. We
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