Source/Drain Overlap Length Dependence of VT in Thin Film Transistor on a-IGZO Channel Deposited by RF and DC Sputtering
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1108-A09-13
Source/Drain Overlap Length Dependence of VT in Bottom Gated Thin Film Transistors on a-IGZO Channel Deposited by RF and DC Sputtering Dong-Ho Nama, Kwang-il Choia, Sung-Soo Parka, Jae-Kyeong Jeongb and Ga-Won Leea,* a b
Dept. of Electronic Engineering, Chungnam National University, Korea
Corporate R&D Center, Samsung SDI Co., LTD, 428-5, Gongse-Dong, Kiheung-Gu, YonginSi, Gyeonggi-Do 449-902, Korea Tel:+82-42-821-5666, Fax:+82-42-823-5944, Email: [email protected]
ABSTRACT We have investigated the threshold voltage (VT) variation of the bottom gated a-IGZO TFTs according to the various source/drain overlap length (3um ~ -3um). As the source/drain overlap length decreases to negative value forming the offset, VT of a-IGZO TFTs is increased and subthreshold slop and field-effect mobility is deteriorated due to the increased series resistance of the offset region. Besides, the VT variation increases sharply, which is aggravated as the channel length decreases. In this paper, experimental VT variation has been compared with devices of different channel deposition methods by RF and DC sputtering. When the channel layer is of superior quality, the VT variation can be suppressed but still remains. This means that the source/drain overlap length is very important control parameter for the uniform device characteristics of a-IGZO TFTs. INTRODUCTION The ZnO TFTs have attracted much attention as key component for flexible displays because they can be fabricated on plastic substrates at low temperature and exhibit/it good electrical performance [1-2] (e.g.. high field effect mobility). However, the ZnO films are polycrystalline with grain boundaries even if formed at room temperature, which deteriorate the uniformity of TFT characteristics [3]. Recently, a few research groups have reported high performance amorphous indium-gallium-zinc oxide (a-IGZO) TFTs to solve the native problem of nonuniformity of ZnO TFTs [4]. However, the device parameter variation can be caused by the fabrication process as well as material itself. Especially, self-aligned source/drain formation is difficult in bottom gate TFTs which have been used as the pixel transistors of display like as active matrix liquid crystal displays and organic light emitting diode display. Therefore, there exists misalignment during source/drain photolithography, which can affect electrical characteristics of transistors. So far, there are few researches on the process parameter effects on the variation of a-IGZO TFT characteristics. In this paper, we focus on the effect of the source/drain overlap length on VT variation of aIZO TFTs with differentiating channel deposition methods. EXPERIMENT Fabrication of devices
The experimental structures for this work are n-type a-IGZO TFT with the bottom gate and top contact. MoW (200nm) was deposited as a gate metal and patterned by photolithograpy on a SiO2/glass substrate. Then, SiNx (200nm) film was deposited by plasma enhanced chemical vapor deposition as a gate insulator. Subsequently, the a-IGZO film with a th
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