Suppression of leakage current in carbon nanotube field-effect transistors
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TRACT Carbon nanotube field-effect transistor (CNT FET) has been considered as a promising candidate for future high-performance and low-power integrated circuits (ICs) applications owing to its ballistic transport and excellent immunity to short channel effects (SCEs). Still, it easily suffers from the ambipolar property, and severe leakage current at off-state originated from gate-induced drain leakage (GIDL) in CNT FETs with small bandgap. Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs, there is still a lack of the structure with excellent scalability, which will hamper the development of CNT FETs toward a competitive technology node. Here, we explore how the device geometry design affects the leakage current in CNT FETs, and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional (2D) TCAD simulations. Among all the proposed structures, the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process. According to the simulation results, the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/µm and an on-current as high as about 2.1 mA/µm at a supply voltage of –1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.
KEYWORDS carbon nanotube, field-effect transistor, leakage current, TCAD simulation, narrow-bandgap semiconductor
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Introduction
Moore’s law has been promoting faster and more powerful integrated circuits (ICs) based on scaling down the complementary-oxide-semiconductor (CMOS) field-effect transistors (FETs) [1–4]. At the sub-20 nm technology nodes, short channel effects (SCEs) have become the dominant mechanisms to hinder the development of CMOS transistors [5–8]. Then new device configurations and emerging channel materials must be adopted to conquer SCEs and push the further development of ICs. Due to the ultra-high carrier mobility and quasi-ballistic transport, CNT has been considered as a promising channel material for constructing the future FETs [9–12]. Notably, CNT’s atomic-thickness body (1–2 nm) and unidirectional thermal velocity (4.1 × 107 cm/s), which is three times higher than that of silicon, enable it possible to achieve high gate efficiency and large on-state current at the same time [13–15]. As a result, CNT FETs have been experimentally demonstrated to be scaled down to 5 nm gate length and exhibit the intrinsic performance outperforming Si CMOS FETs at a similar gate length [16]. Since an effective and stable doping method is absent in CNTs, doping-free CMOS technology has been developed and widely used to fabricate high-performance CNT FETs. Palladium (Pd) and scandium (Sc) are respectively used as source/drain (S/D) to realize p- and n-FET through selectively injecting hole or electron int
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