The effect of ion milling on the morphology of ramp-type Josephson junctions
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The effect of ion milling on the morphology of ramp-type Josephson junctions Dave H. A. Blank and Horst Rogalla Low Temperature Division, Department of Applied Physics, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands (Received 21 April 1997; accepted 8 August 1997)
Artificial barriers in Josephson junctions make it possible to change the height and width of the barrier independently. This technique can be realized in high-Tc Josephson junctions using the ramp technique. In this article the fabrication of ramp-type junctions is discussed and the importance of the morphology of the ramp is pointed out. Detailed investigations are described which address the surface roughness and the damage due to ion-beam structuring of ramps. It is shown that hard masks can significantly improve the ramp quality by reducing the ion impact angle. Furthermore, annealing of the so structured ramps leads to unit cell steps enforcing a step-flow growth mode.
I. INTRODUCTION
The possibility to apply artificial epitaxial barriers makes ramp-type junctions especially attractive as Josephson junctions in high-Tc superconducting electronics.1 A-b-plane geometry allows for a wide range of coupling strengths between junction electrodes, from direct superconducting coupling over tunneling to insulation, depending on the height and thickness of a homoepitaxial barrier. In contrast, c-axis coupling is much weaker and in general Josephson currents cannot be observed. Deposition of layers from the top gives a much higher degree of control, because in that case standard deposition methods can be used and one can easily vary the barrier thickness and material. Ramptype junctions combine in that sense the advantages of a planar design with the strong coupling in the a-b-plane. Since the first publication on ramp-type junctions, immense progress has been made. The characteristics of the junctions can be tailored by changing the barrier thickness and/or doping the barrier material, e.g., Ga-doping of PrBa2 Cu3 O72d . However, the electrical characteristic of the ramp-type junction is still not reproducible enough for medium scale integration (more than 100 junctions on one chip). This holds especially true if one compares the junction spread from run to run. One of the reasons is the quality of the ramp, which relies a great deal on an ex-situ etching procedure. Furthermore, the homoepitaxial growth of the barrier material on (etched) ramps is not trivial. With the present fabrication methods a minimum thickness of 8–10 nm is required to ensure coverage of the whole junction area.2 Another aspect is the possible segregation of doped species leading to inhomogeneous electrical properties. In this contribution we are looking in more detail into the materials aspects of the ramp-type junction. Each process step has been studied extensively to improve the 2952
http://journals.cambridge.org
J. Mater. Res., Vol. 12, No. 11, Nov 1997
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reproducibility and quality of
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