Thermal Management in High-Density, Stacked-Die, Multi-chip Modules
- PDF / 286,178 Bytes
- 7 Pages / 612 x 792 pts (letter) Page_size
- 95 Downloads / 202 Views
0968-V05-08
Thermal Management in High-Density, Stacked-Die, Multi-Chip Modules Thomas Marinis, Dariusz Pryputniewicz, Caroline Kondoleon, and Jason Haley Draper Laboratory, 555 Technology Square, Cambridge, MA, 02139
ABSTRACT Very high density multi-chip modules (MCM) are being manufactured by tiling an alumina substrate with IC chips and passive components, laminating a film of Kapton over them, laser drilling vias to their I/O pads, and interconnecting them with photo patterned, copper metallization. Additional layers of components and interconnects are added on top of the base layer, as needed, to allow greater integration of large circuits. Current products are typically two layers of chips and seven layers of interconnect. As higher power applications have emerged and the power density of IC chips has increased, thermal management has become a significant factor impacting module design. We have been conducting a thermal modeling effort to map the design space for this technology. Our principal objective is to define and evaluate low thermal impedance (heat removal) configurations for a given chip set. A second objective is to determine what gains in module performance might be realized by improvements in material properties or changes in the relative thicknesses of dielectric and metal layers. INTRODUCTION The fabrication process used to build multi-chip modules with deposited thin film interconnect (MCM-D modules), of the type discussed in this paper, has been described previously.1 For this analysis, the module design consisted of two chips (“top” and “bottom” chips) with two routing layers between them. As stated previously, a typical module consists of seven layers of interconnect, however, we modeled two layers since the direction of heat flow would only go through these two routing layers to the thermal sink. A cross sectional view (not to scale) of the layer stack up, and overall dimensions used in the analysis is shown in Figure (1). Specifics of the materials used are shown in Figure (2). Additionally, for this analysis, the layers of interconnect are modeled as composite materials based on the amount of interconnect copper located within the interconnect layers. Furthermore, adjacent to each chip, there is an area of glue and voids, which serves as a region between chips to accommodate variations in size and placement accuracy. This has been seen to be the region of highest thermal impedance in the module. Two complementary techniques were used to construct thermal models of this assembly. A one-dimensional model consisting of a series of resistor elements was implemented in a spreadsheet program to compute temperature distributions along the y-axis of Figure (1). A two dimensional, finite element model (FEM) was used to map temperature distributions in the x-y plane of Figure (1). The spreadsheet program was used to quickly evaluate different stack up geometries and material combinations and to validate FEM results. The FEM model was used to capture and evaluate various heat spreading strategies.
Data Loading...
