Toward a general framework for jointly processor-workload empirical modeling
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Toward a general framework for jointly processor‑workload empirical modeling Hamed Sheidaeian1 · Omid Fatemi1 Accepted: 20 October 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The complexity of state-of-the-art processor architectures and their consequent vast design spaces have made it difficult and time-consuming to explore the best configuration for them. Design space exploration (DSE) refers to systematic analysis and pruning of unwanted design points based on parameters of interest. DSE requires analysis and estimation of performance criteria of design points. A more accurate estimation produces a more efficient target design. A typical estimation method is machine learning approaches based on statistical inference, also known as empirical modeling, which requires only a limited number of simulations. Undoubtedly, an empirical model finds the optima much faster than using cycle-accurate simulations and is much more accurate than employing analytical models. For that purpose, our paper proposes a general methodology and a framework to find an appropriate and most accurate empirical model to estimate the performance of general-purpose or embedded multiprocessors running multithreaded workloads. This framework consists of three main steps: (1) Workload characterization and clustering, (2) Finding optimal model, and (3) Estimating the performance of a new workload outside the training set. These optimal performance prediction models could be utilized in the process of exploring the architectural design space. An experimental case is also tested using this framework for feasibility purposes. Validation experiments show MAEs less than 10% for this case. Keywords Processor modeling · Empirical models · Workload clustering · Combined Algorithm Selection and Hyper-parameters Optimization · Performance Estimation
* Hamed Sheidaeian [email protected] Omid Fatemi [email protected] 1
Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran
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H. Sheidaeian, O. Fatemi
1 Introduction The most critical constraints on the processor design include performance, power, and area budget. Performance is a significant criterion in computer architecture. Hence, it is essential to determine which hardware platform running target programs will result in the highest performance. The goal of DSE is to choose the best and most appropriate configuration for processors considering programs that should run on it. Although it is possible to find optimum processor configuration at the circuit level, it is very time-consuming. Therefore, system-level design methods are used to estimate the performance of programs on different architectures in a reasonable time and budget and to reduce the time of exploration in the design space. So, various processor modeling techniques can be employed for high-level performance estimation [1]. The main challenge is the complexity of exploring the design space (all of the possible selectable configurations) due to i
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