Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder
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Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder J. Jean Jenifer Nesam 1 · S. Sankar Ganesh2 Received: 18 November 2019 / Revised: 20 September 2020 / Accepted: 25 September 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The delay owing to the generation of odd multiples (± 3) in Radix-8 Booth recoding is minimized in this paper using carry resist adder (CRA). CRA is intentionally developed for performing the exact addition of ± 1 and ± 2 without carry propagation. The theoretical delay analysis proves that the 8-bit CRA reduces 86.26% of delay when compared to the conventional Carry Propagate Addition (CPA) methods. Subsequently, the relative comparisons of CRA with various approximation-based recoding show that the CRA consumes fewer area, power and critical path delay. Further, the 8 × 8 and 16 × 16 signed binary multiplication using CRA-based Radix-8 Booth recoder is developed and synthesized on TSMC 65nm CMOS standard cell library. Also, the trade-off between area, power, delay and accuracy is verified for the proposed design using truncation. Finally, the CRA-based truncated Radix-8 Booth 8 × 8 multiplier is applied to the color space conversion for quantifying its amicability in imaging. The PSNR and MSE are used to evaluate the quality of the resultant image and show better performance than other existing approximated as well as truncated Radix-8 Booth multipliers. Keywords Radix-8 Booth · Carry resist adder (CRA) · Exact Booth recoding · Minimized delay adder · Truncated multiplier
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S. Sankar Ganesh [email protected] J. Jean Jenifer Nesam [email protected]
1
Electronics and Communication Engineering, Siddharth Institute of Engineering and Technology, Puttur, A.P 517583, India
2
School of Electronics Engineering, Vellore Institute of Technology, Vellore, Tamil Nadu 632014, India
Circuits, Systems, and Signal Processing
1 Introduction Multipliers are the key modules in numerous signal and image processing applications. The speed of multiplier defines the application’s speed. Booth algorithm helps to achieve fast multiplication using Partial Product (PP) row reduction [2]. Radix-based Booth reduces the PP height on different levels based on their recoding nature. Among them, Radix-4 is considered more attractive due to its addition-free recoding operation. Radix-4 Booth recoding (R4BR) reduces the number of PP rows from n to n2 + 1 for n-bit multiplier. Its coefficients such as ± 0, ± 1 and ± 2 generate the PPs using shifters and inversion operations. Higher Radix-based Booth demands adder along with shifter and inversions. Albeit Radix-8 Booth further reduces the PP height from n to n3 + 1, it slows owing to the odd multiple generations in its recoding phase. It uses the coefficients such as ± 0, ± 1, ± 2, ± 3 and ± 4. The ± 3 is considered as odd multiples, and the adder needs to add ± 1 and ± 2 for its computation. Adder involved in this odd multiple generation increases the delay and limits its re
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