Re-Examining The Physical Basis of Pattern Density and Step Height CMP Models
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RE-EXAMINING THE PHYSICAL BASIS OF PATTERN DENSITY AND STEP HEIGHT CMP MODELS Xiaolin Xie, Tae Park, Brian Lee, Tamba Tugbawa, Hong Cai and Duane Boning Microsystems Technology Laboratories, MIT 60 Vassar St, Bldg 39-567, Cambridge, MA 02139 ABSTRACT Our group has proposed several chip-scale CMP models, with key assumptions including the notion of planarization length in the pattern density model [1], and step height dependent polishing rate in the density step height model [2]. In the effective density model, planarization length is the characteristic length of an elliptic weighting function based on the long-range pad deformation and pressure distribution during CMP. This semi-physical model is often adequate and usually gives a fitting error of a few hundred angstroms. As ever-shrinking device size pushes for tighter control of post CMP uniformity, however, we need a chip-scale CMP model with better accuracy. In this work, we re-examine the physical basis for averaging weighting functions and step height dependence, particularly in the context of contact mechanics based model formulations. The comparison of the two models confirms that the analytical density and step height models can be viewed as approximations to the contact wear model. The study also suggests a new dependence of contact height on line space and pattern density. INTRODUCTION In chemical–mechanical polishing (CMP), excellent planarization (i.e., reduction in step height) of individual patterned features is achieved; however, global nonplanarity is unfortunately created due to differences in the underlying pattern, resulting in nonuniform oxide thickness across the die. The ability to predict the post-CMP oxide thickness for arbitrary chip layouts is critical for CMP and deposition process optimization, layout screening or density design rule checking, pattern density equalization (e.g., dummy fill), process control, and circuit impact analysis. CMP models have usually focused either on wafer scale considerations (e.g., kinematic models of relative velocity, fluid flow models, pressure models), feature scale effects [3] or on layout pattern effects. Among the more promising approaches are contact wear or pad pressure based models by Chekina et al. [4], and Yoshida [5], which seek to solve for the local displacements and pressures of an elastic polishing pad in contact with the patterned wafer surface. Such models require time-stepped evolution of the surface, as well as discretization down to the size of the features of interest, and are computationally intensive if applied across an entire product chip. An alternative approach has been proposed by Stine et al. in which analytic solutions are possible, based on calculation of the effective pattern density across the chip [6]. This approach is coupled to a rapid characterization methodology using test patterns and test masks, so that the essential model parameters can be estimated for a given CMP process [7]. The effective pattern density model builds on a key concept of planarization leng
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