Recent Advances in 3D Integration at IMEC
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0970-Y01-02
Recent Advances in 3D Integration at IMEC Piet De Moor, Ruythooren Wouter, Soussan Philippe, Swinnen Bart, Baert Kris, Van Hoof Chris, and Beyne Eric IMEC, Kapeldreef 75, Leuven, B-3001, Belgium
ABSTRACT IMEC is focusing its 3D-integration technology developments in 3 distinct directions: 3D-System-in-a- Package (3D-SiP), 3D-Wafer-Level-Packaging (3D-WLP) and 3D-Stacked-IC (3D-SiC). First, the background of these separate approaches will be given. Next the materials and technologies involved, the typical characteristics and the ongoing developments will be discussed. Finally, the roadmap for the 3D-integration in IMEC will be presented. INTRODUCTION Advantages of 3D integration A large number of good reasons to use 3D integration are present today [1-3]. Summarizing, the main drivers are: performance enhancement and form factor reduction. In terms of performance, 3D stacked dies can benefit of (relatively) short interconnects between e.g. functional blocks, as compared to fairly long horizontal global interconnects on a classical CMOS chip. Even more important (and extending the field of CMOS by far) is the concept of heterogeneous integration: instead of combining different technologies on one die (which is in general costly – if feasible at all), dies emerging from different technologies can be assembled using short interconnects. This has two major advantages: first, due to the drastically reduced parasitic capacitance, higher speed and lower power consumption is obtained. Moreover, the two (or more) different technologies can be optimized independent in terms of technology and specifications. Historical examples where this vertical integration is used are detector systems, such as X-ray or infrared detectors – often using non-Si materials - hybridized on readout circuits. But there are many other applications of heterogeneous integration, such as logic and memory, MEMS sensors or actuators and read-out electronics. The achievable form factor reduction using 3D-integration is obvious: today’s advanced thinning technology enables Silicon thinning to less than 50 um, enabling very thin yet performing systems. Moreover, as Si becomes flexible at such dimensions, the fabrication of flexible and even stretchable devices become feasible.
Risks Apart from the extra cost involved in 3D-integration, there are a number of risks that could hamper the break-through of 3D-integration. As in standard packaged systems, the reliability needs to be addressed. Moreover, most 3D integrated systems use aggressive substrate thinning, possibly resulting in (catastrophic) influence on the device properties. There are a number of yield considerations as well – which translate directly into cost. Finally, the thermal management of a 3D stack will require even more attention than that of a classical package. Reliability of 3D stacks depends very much on the design, materials and technology used. The problems are however quite similar to the standard packaging and hybridization reliability issues: mismatch of coefficient of
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