Residual Stress in CVD-grown 3C-SiC Films on Si Substrates
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1069-D03-05
Residual Stress in CVD-grown 3C-SiC Films on Si Substrates Alex A. Volinsky1, Grygoriy Kravchenko1, Patrick Waters1, Jayadeep Deva Reddy1, Chris Locke2, Christopher Frewin2, and Stephen E. Saddow2 1 Department of Mechanical Engineering, University of South Florida, 4202 E. Fowler Ave. ENB118, Tampa, FL, 33620 2 Department of Electrical Engineering, University of South Florida, 4202 E. Fowler Ave. ENB118, Tampa, FL, 33620 ABSTRACT Having superior mechanical properties, 3C-SiC is one of the target materials for power MEMS applications. Growing 3C-SiC films on Si is challenging, as there is a large mismatch in lattice parameter and thermal expansion between the SiC film and the Si substrate that needs to be accommodated, and results in high residual stress. Residual stress control is critical in MEMS devices as upon feature release it results in substantial deformation. 3C-SiC single crystalline films were deposited on 50 mm (100) and (111) Si substrates in a hot-wall CVD reactor. The film tensile residual stress was so high that it fractured on the (111) Si wafer. The resulting film thickness on the (100) Si wafer was non-uniform, having a linear profile along the growth direction. This presented a challenge of using the substrate curvature method for calculating residual stress. Finite Element Method correction was applied to the Stoney’s formula for calculating the residual stress along the wafer radius. Suggestions for reducing the amount of residual stress are made. INTRODUCTION SiC is the material of choice for power MEMS applications, since it has much better mechanical performance at high temperatures, compared to Si. Deposition and processing techniques must be mastered before a functioning device can actually be built. It is advantageous to deposit SiC on Si wafers due to their high quality and low cost, in comparison to SiC substrates. However, one has to overcome the 22% lattice mismatch between the 3C-SiC film and the (100) Si substrate, and additional 8% mismatch in thermal expansion. Any temperature variation will cause stress. 3C-SiC films on (111) Si wafers have larger residual stress, although there is a slightly smaller lattice mismatch of about 19.7%. In both instances 3C-SiC can be hetero-epitaxially grown on a highly defective SiC buffer layer formed during the so-called carbonization step, which could accommodate some of the mismatch strain. EXPERIMENT Single crystal 3C-SiC films were grown hetero-epitaxially in a hot-wall chemical vapor deposition (CVD) reactor on (100) and (111) 50 mm Si substrates [1]. The 3C-SiC on Si deposition process was developed using the two step carbonization and growth method. C3H8 and SiH4 were used as the precursors to provide the carbon and silicon sources, respectively. The carrier gas was ultra-high purity hydrogen, purified in a palladium diffusion cell. Prior to growth, the substrates were prepared using the RCA cleaning method [2], followed by a 30 second immersion in diluted hydrofluoric acid to remove the surface oxide and possible contaminants.
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