Retargetable Compiler Technology for Embedded Systems Tools and Appl
It is well known that embedded systems have to be implemented efficiently. This requires that processors optimized for certain application domains are used in embedded systems. Such an optimization requires a careful exploration of the design space, inclu
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Retargetable Compiler Technology for Embedded Systems Tools and Applications by
Rainer Leupers and Peter Marwedel University of Dortmund
SPRINGER-SCIENCE+BUSINESS MEDIA, B.V.
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4757-6420-8 (eBook) ISBN 978-1-4419-4928-8 DOI 10.1007/978-1-4757-6420-8
Printed on acid-free paper
All Rights Reserved © 2001 Springer Science+Business Media Dordrecht Originally published by Kluwer Academic Publishers, Boston in 2001 No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without written permission from the copyright owner.
To Carl and Veronika, M alte, Gesine, and Ronja
Contents
ix
Preface 1. INTRODUCTION 1.1 Embedded systems and their characteristics 1.2 Efficient hardware 1.3 Efficient software 1.3.1 How to specify embedded system software? 1.3.2 Efficient compilers 1.3.3 Retargetable compilers
1 1 3 4 4 5 6
2. COMPILERS IN EMBEDDED SYSTEM DESIGN 2.1 Design flow and hardware/software codesign 2.2 Design space exploration 2.2.1 Levels in the design space 2.2.2 Algorithm selection 2.2.3 Options for implementing algorithms 2.2.4 Process mapping and HW /SW partitioning 2.2.5 Memory system design 2.2.6 Instruction set options 2.2.6.1 Design of VLIW machines 2.2.6.2 Design of non-VLIW machines 2.2.6.3 Word length optimization 2.2.6.4 Register file sizing 2.2.7 Micro-architectural options 2.3 Design verification
9 9 11 11 14 15 15 17 18 18 21 21 23 24 26
3. SOME COMPILER TECHNOLOGY BACKGROUND 3.1 Front end 3.2 Intermediate representation 3.3 Backend 3.3.1 Code selection
27 28 34 40 40
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RETARGETABLE COMPILER TECHNOLOGY
3.3.2 3.3.3 3.3.4 3.3.5 3.3.6
Scheduling Register allocation Address code optimization Phase coupling issues Peephole optimization
44 50 53 56 58
4. HISTORICAL OVERVIEW 4.1 Contributions from the compiler community 4.1.1 UN COL 4.1.2 Code generation for expressions 4.2 Contributions from microprogramming 4.2.1 Motivation 4.2.2 Early work 4.2.3 First retargetable microcode compilers 4.2.4 The MIMOLA project
59 59 59 60 61 62 62 63 64
5. RETARGETABLE COMPILER CASE STUDIES 5.1 Retargetable compilers for GPPs 5.1.1 GCC 5.1.2 LCC 5.1.3 Marion 5.1.4 PAGODE 5.1.5 SUIF /Machine SUIF 5.1.6 Zephyr/VPO 5.1.7 LANCE 5.2 Retargetable compilers for DSPs 5.2.1 CBC 5.2.2 RED ACO 5.2.3 CodeSyn/FlexWare 5.2.4 SPAM 5.2.5 RECORD 5.3 Retarget able compilers for VLIWs 5.3.1 ROCKET 5.3.2 IMPACT 5.3.3 Trimaran 5.3.4 Trimedia 5.3.5 AVIV 5.3.6 Mescal 5.4 Retargetable compilers for ASIPs 5.4.1 MSSQ 5.4.2 PEAS 5.4.3 Valen-C 5.4.4 EXPRESS 5.4.5 BUILDABONG 5.5 Special retargetability techniques
67 68 68 71
75 76
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79 81 84 84 87 89 91 95 98 98 99 100 102 103 105 105 105 110 113 114 116 118
Contents
5.5.1 Code generation methods 5.5.1.1 Balakrishnan's microcode compiler 5.5.1.2 Mavaddat's formal language approach 5.5.1.3 Langevin's automat
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