SBOX under PVT variation
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SBOX under PVT variation Abhishek Kumar1
•
Suman Lata Tripathi1
Received: 14 January 2020 / Revised: 26 June 2020 / Accepted: 17 July 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The process corner refers to the variation into fabrication parameters used to apply during integrated circuit design to the semiconductor wafer. Inconsistency during design and deviation of voltage and temperature during its operation widens the worst-case margin and significantly degrades the performance. The impact of variation is more pronounced at smaller technology node (\ 90 nm). In CAD-tool variability are modeled as fast and slow MOS transistors. Design parameters must be validated at all corners before sending them to be fabricated. In this work, the schematic of the substitution box (SBOX) implemented with the cadence tool at CMOS 45 nm technology node and their variability analyzed. The impact of variation onto the SBOX parameter (power, delay, and energy) has presented at process corners with ± 10% variation in supply voltage and temperature (27–80 °C). The simulation result shows that the best choice of SBOX implementation when NMOS tends to get fast and PMOS tends to get slow. Keywords PVT SBOX NED NSD Process corner AES
1 Introduction Cryptography is an art to secure data transmission from unauthorized use. Advanced Encryption Standard (AES) adopted as an encryption standard by the National Institute of Standard Technology (NIST) in 2001 [1]. Since then it has been used to secure multiple electronic systems and algorithms. AES iterative process that repeats a set of functions for a definite number of rounds depending on the key size discussed in [2, 3]. During encryption input text applied into a set of functions repeated n number of times; where values of n is 10, 12 and 14 depending on the key size 128, 192 or 256, respectively. Each round of AES processed through four significant blocks of AES that are presented in Fig. 1. (a) AddRoundKey: It represents a logically XORed input text with a round key, (b) Shift-row: It shifts the content of each byte to the left by 1, 2 or three positions depending on the row sequence, (c) MixColumn: It implements matrix multiplication with a constant value, (d) Sub Byte: It is a 1-byte nonlinear substitution. SubByte
& Abhishek Kumar [email protected] 1
School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, India
is the most critical block in AES; it includes nonlinearity in the encryption process. In this step, input byte replaced by one of 256 nonlinear bytes arranged as 16 * 16 matrix is known as a substitution box (SBOX). SBOX substitutes a nonlinear byte for each input byte. Two popular structure of SBOX is (1) lookup table (LUT) method where precomputed value stored in memory and (2) computation method where each nonlinear byte to substituted computed in composite field arithmetic. LUT-SBOX architecture requires 256 bytes stored in ROM and input byte acts an address bus. However, thi
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