Scalable IC Platform for Smart Cameras
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Scalable IC Platform for Smart Cameras Richard P. Kleihorst Philips Research Laboratories, Professor Holstlaan 4, 5656 AA Eindhoven, The Netherlands Email: [email protected]
Anteneh A. Abbo Philips Research Laboratories, Professor Holstlaan 4, 5656 AA Eindhoven, The Netherlands Email: [email protected]
Vishal Choudhary Philips Research Laboratories, Professor Holstlaan 4, 5656 AA Eindhoven, The Netherlands Email: [email protected]
Harry Broers Philips Industrial Vision, P.O.Box 218, 5600 MD Eindhoven, The Netherlands Email: [email protected] Received 19 December 2003; Revised 24 January 2005 Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas, software and IC development. In order to reduce cost, it is worthwhile to invest in a single architecture that can be scaled for the various application areas in performance (and resulting power consumption). In this paper, we show that the combination of an SIMD (singleinstruction multiple-data) processor and a general-purpose DSP is very advantageous for the image processing tasks encountered in smart cameras. While the SIMD processor gives the very high performance necessary by exploiting the inherent data parallelism found in the pixel crunching part of the algorithms, the DSP offers a friendly approach to the more complex tasks. The paper continues to motivate that SIMD processors have very convenient scaling properties in silicon, making the complete, SIMDDSP architecture suitable for different application areas without changing the software suite. Analysis of the changes in power consumption due to scaling shows that for typical image processing tasks, it is beneficial to scale the SIMD processor to use the maximum level of parallelism available in the algorithm if the IC supply voltage can be lowered. If silicon cost is of importance, the parallelism of the processor should be scaled to just reach the desired performance given the speed of the silicon. Keywords and phrases: smart cameras, IC architectures, image processing, SIMD, parallel processing, architecture scaling.
1. INTRODUCTION Real-time video processing on (low-cost and low-power) programmable platforms is now becoming possible thanks to advances in integration techniques [1, 2, 3, 4]. This is relevant to a number of applications such as mobile communications, home robotics, and even industrial image processing [5, 6]. It is important that these platforms are programmable since new applications for smart cameras emerge every month. The complexity (and possible error-proneness) of the algorithms and the fickleness of real-life scenes are also strongly motivating complete programmability. Repeatedly building application-specific ICs or weakly programmable ICs is simply too costly and by far not sufficient for this changing market. It seems like a daunting task to create programmable hardware that is able to process multimillion pixels per
second for complex decision tasks. However, we will show in this paper
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