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D5.1.1

Semiconductor Nanocrystal Floating-gate Memory Devices P. Dimitrakis and P. Normand Institute of Microelectronics, NCSR ‘Demokritos’ 15310 Aghia Paraskevi, Greece ABSTRACT Current research directions and recent advances in the area of semiconductor nanocrystal floating-gate memory devices are herein reviewed. Particular attention is placed on the advantages, limitations and perspectives of some of the principal new alternatives suggested for improving device performance and reliability. The attractive option of generating Si nanocrystal memories by ion-beam-synthesis (IBS) is discussed with emphasis on the ultra-low-energy (ULE) regime. Pertinent issues related to the fabrication of low-voltage memory cells and the integration of the ULE-IBS technique in manufactory environment are discussed. The effect on device performance of parasitic transistors that form at the channel corner of shallow trench isolated transistors is described in details. It is shown that such parasitic transistors lead to a substantial degradation of the electrical properties of the intended devices and dominates the memory behavior of deep submicronic cells. INTRODUCTION To overcome the performance and scaling limitations of current semiconductor memories and successfully follow market expansion in computer and wireless communication devices, a number of new memory technologies are being actively explored (for a recent review see Ref. [1]). A promising route for low-cost ultra-dense low-power data storage lies in the use of singleMOSFET memory-cell structures where the charge storage medium is composed of mutually isolated nodes in place of the polysilicon layer employed in conventional floating-gate (FG) nonvolatile memory (NVM) devices. Such discrete nodes reduce the problems of charge loss encountered in FG NVMs, allowing for thinner injection oxides and hence, higher write/erase speeds, better endurance and lower charging voltages. Today, two types of discrete node memories are actively examined: The polySilicon-blocking Oxide-Nitride-tunneling OxideSilicon (SONOS) memory and the nanocrystal memory (NCM). The former makes use of traps (dangling bonds) randomly distributed in a nitride layer, while the latter employs a high-density (typically in the range 2x1011 to 2x1012 cm-2) of laterally uncoupled nanocrystal dots with diameters of 2-10nm embedded in a dielectric matrix. Nitride-based memories [2-5] have been studied for many years and are widely used in the industry for multiple applications. While advancements in ultra-thin dielectrics have placed SONOS technology as a potential candidate for scaled-NVMs, charge storage in a nitride layer imposes serious limitations on the cell operating voltages and speeds. NC memories [1, 6-9] have relatively short history and product-oriented development is not activated yet. These devices present significant advantages over SONOS memories in terms of programming/erase speeds, trapping probability, potential well depth and scaling limitation. In addition, Coulomb blockade and quantum confin